Filtering circuit, phase consistency judging circuit and delay locked loop

Abstract

The invention discloses a filter circuit, a phase consistency judging circuit and a delay locked loop. The filter circuit includes: a clock selection unit configured to transmit a first clock or a clock whose frequency is higher than a second clock in response to a frequency signal. a second clock clocked low as an operating clock; and a filter configured to filter the input signal and generate a filtered signal synchronously with the operating clock.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2011-0140494 filed on December 22, 2011, the entire contents of which are hereby incorporated by reference. technical field [0003] Exemplary embodiments of the present invention relate to a filter circuit, a phase consistency judgment circuit, and a delay locked loop. Background technique [0004] Circuit devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) perform transmission of various signals and data using an internal clock synchronized with an external clock used in an external system. Although a clock input to a circuit device is initially applied in a state of being synchronized with an external clock, it is delayed while passing through various components in the device, and is not synchronized with the external clock when being input to the outside of the device. Thus, for stable transmission of signals and data, the internal cl...

AI Technical Summary

Problems solved by technology

As the length of the filter depth becomes longer, the possibility of half-locking increases

Images