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Network-on-chip-based many-core chip management structure fault tolerance method

An on-chip network and management method technology, applied in hardware redundancy for data error detection, response error generation, etc., can solve problems such as the scrapping of the entire chip and the inability to maintain the chip to continue to work.

Inactive Publication Date: 2014-12-03
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to solve the problem that if some important management cores and their redundant cores all fail, even if there are many remaining cores on the chip, the continued operation of the chip cannot be maintained, resulting in the premature scrapping of the entire chip. The invention provides a fault-tolerant method for many-core chip management structure based on network-on-chip

Method used

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  • Network-on-chip-based many-core chip management structure fault tolerance method
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  • Network-on-chip-based many-core chip management structure fault tolerance method

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specific Embodiment approach 1

[0010] Specific implementation mode 1: The fault-tolerant method of many-core chip management structure based on network-on-chip described in this implementation mode,

[0011] The network-on-chip-based many-core chip management structure includes multiple cores, the multiple cores include master control cores and redundant cores at various levels, and the redundant cores are divided into fixed redundant cores and dynamic redundant cores. Core, group the management structure of the chip, and use the management method of mutual monitoring within the group for each group; adopt the self-adaptive management method for all cores of the chip; use the election management method in each group; The core adopts the management method of hardware self-awakening, and the management method of software self-awakening is adopted for the dynamic redundant core.

specific Embodiment approach 2

[0012] Specific implementation mode two: combination figure 1 Describe this embodiment, this embodiment is to further limit the fault-tolerant method of the network-on-chip-based many-core chip management structure described in the first embodiment,

[0013] The method for grouping the management structure of the chip is as follows:

[0014] The chip management structure is grouped according to the jurisdiction areas of the main control cores at different levels: each group includes a group leader core and multiple team member cores, and the team leader core is the main control core at a certain level in the chip. If the team member core is at the bottom of the chip management structure, then the team member core is the computing core, otherwise, the team member core is the master control core of the next level of the team leader core; The main control core also includes a redundant core; the computing core also includes a redundant core;

[0015] Each group obtained after t...

specific Embodiment approach 3

[0018] Embodiment 3: This embodiment further limits the fault-tolerant method of the many-core chip management structure based on the network-on-chip described in Embodiment 2.

[0019] The method for adopting adaptive management to all cores of the chip is as follows:

[0020] The responsibilities of the main control core of each group at least include redundant core management and dynamic grouping, and all cores of the chip dynamically select a corresponding management method according to their current roles in the management hierarchy.

[0021] Such as figure 1 As shown, each level of the main control core has its own responsibilities.

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Abstract

The invention discloses a network-on-chip-based many-core chip management structure fault tolerance method, and relates to a fault tolerance method. The method is used for solving the problem that certain important management cores and redundant cores all go wrong, and the continues work of a chip can not be kept even if a plurality of cores remained on a piece, so that the chip is scraped too early. The method comprises the following steps that: the network on chip-based many-core chip management structure comprises a plurality of cores, the plurality of cores include master control cores and redundant cores in various levels, the redundant cores are divided into fixed redundant cores and dynamic redundant cores, the management structure of the chip is grouped, and an intra-group monitoring management method is used for each group; an adaptive management method is used for all the cores of the chip; an election management method is used for each group; and an automatic hardware waking-up management method is used for the fixed redundant cores, and an automatic software waking-up management method is used for the dynamic redundant cores. The fault tolerance method is used for the fault tolerance for the management structure of the many-core chip.

Description

technical field [0001] The invention relates to a fault-tolerant method, in particular to a method for fault-tolerant management structure of many-core chips based on a network on chip. Background technique [0002] With the improvement of semiconductor chip integration capabilities and the improvement of people's requirements for chip processing capabilities, the number of processor cores integrated on a single chip has increased from dozens to hundreds. Judging from the current trend, the number will continue to increase, and the number of cores integrated in future chips may exceed one thousand. For this kind of many-core (manycore, which refers to many computing cores integrated on a single chip) chip, its on-chip interconnection currently mostly uses a network-on-chip (NoC, which is a network-on-chip Internal on-chip interconnection network), and its resource management mostly adopts a hierarchical management structure. In resource management of many-core chips based ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/16
Inventor 王进祥吴子旭付方发路禹
Owner HARBIN INST OF TECH
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