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Memory cell, method of forming memory cell, and method of operating memory cell

A storage unit and storage element technology, applied in information storage, static memory, read-only memory, etc., can solve problems such as failure

Inactive Publication Date: 2016-12-28
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The challenge in STT-MRAM arrays is that although it is often possible to use a combination of erased and programmed reference cells to generate reference currents (which may be useful for reading the state of selected cells), if the entire memory current distribution is wide or close, they may fail

Method used

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  • Memory cell, method of forming memory cell, and method of operating memory cell
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  • Memory cell, method of forming memory cell, and method of operating memory cell

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Embodiment Construction

[0017] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0018] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0019] The word "over" as used herein to describe a feature (e.g., layer) formed "over" a side or surface may be used to mean, may be "directly on" the side or surface to which it is implied ( eg, in direct contact therewith) forms the feature (eg, the layer). The word "over" as used herein to describe a feature (such as a layer) being formed "over" a side or surface may be used to mean, may be formed "indirectly on" the implied side or surface The feature, such as the layer, wherein one or more additional layers are arranged between...

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Abstract

Memory cells, methods of forming memory cells, and methods of operating memory cells are disclosed. A memory cell is provided, comprising: a first two-terminal storage element; a second two-terminal storage element; a controller circuit configured to program the first two-terminal storage element to one or more states and programming the second two-terminal storage element to one or more states, wherein the state of the first two-terminal storage element and the state of the second two-terminal storage element are interdependent; and a measurement circuit configured is configured to measure a difference signal between a first two-terminal signal associated with the state of the first two-terminal and a second two-terminal signal associated with the state of the second two-terminal .

Description

technical field [0001] Various embodiments relate generally to memory cells, methods for forming memory cells, and methods for operating memory cells. Background technique [0002] Compared with traditional floating gate FLASH cells, many innovative non-volatile memory NVM applications and concepts (such as magnetoresistive random access memory MRAM, such as resistive random access memory RRAM, such as conductive bridge random access memory CBRAM, such as phase Variable memory PCRAM) suffers from a very small read current window. Over the lifetime of the memory cell, the memory cell may experience an unstable read current window, especially when considering the typically large distribution width in larger cell fields. Until now, attempts have been made to make small read windows available, for example by variable reference, by using stronger error correction codes ECC, complex program algorithms, and by restrictions on specifications such as temperature and number of cycles...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06G11C16/02
CPCG11C11/16G11C11/1673G11C2213/78Y10T29/49117
Inventor W.阿勒斯M.耶弗雷莫夫J.奥特斯泰特C.彼得斯R.韦斯纳
Owner INFINEON TECH AG