Array substrate and manufacture method and display device thereof
A technology for array substrates and substrates, applied in semiconductor/solid-state device manufacturing, optics, instruments, etc., can solve the problems of reducing the aperture ratio of display devices, reducing the aperture ratio of display devices, etc., and achieve the effect of increasing the aperture ratio
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Publication Date
- 2013-09-04
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
Description
technical field
[0001] The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique
[0002] With the development of display technology, touch display devices that integrate input and output terminals have appeared. With the advent of a series of products such as small and light hand-held touch devices, the market demand for touch display devices has surged . Among the various existing touch display devices, the projected capacitive touch device in the capacitive touch device has become the main development direction because of its advantages of real multi-touch and high sensitivity.
[0003] Such as figure 1 As shown, it is an array substrate of a mutual inductive capacitive touch display device in the existing projected capacitive touch screen, and the array substrate includes gate lines 11, data lines 12, gate lines 11 and data lines 12 Pixel electrode 1...
Examples
Embodiment Construction
[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention.
[0030] An embodiment of the present invention provides an array substrate, such as figure 2 As shown, the array substrate includes a gate line 21, a data line 22, a pixel electrode 23 and a thin film transistor 24 arranged in the pixel area defined by the gate line 21 and the data line 22, and a common electrode 25; the array substrate It also includes a first sensing line 26 and a second sensing line 27, the first sensing line 26 and the second sensing line 27 are arranged in parallel on the upper and lower layers, and are all connected to the electrode strips on the common electrode 25. Intersection arrangement; wherein, the first sensing line 26 is located betwee...