A modulo adder

Abstract

The invention discloses a modulo (2n-2k+1) adder, comprising: n-bit HA1 array, n+1-bit HA2 array, n-k-bit HA2 array, n-k-bit LF prefix structure, k-bit LF prefix structure, n-k-bit CA1 array, first OR gate, second OR gate, first AND gate, 1-bit inverter, n-k-2 bit OR array, n-k-2 bit CA2 array, first XOR gate, CA2 processing module, k bits CA1 array and n-bit XOR array. The adder of the present invention is based on the LF prefix structure, and adopts the method of subtracting 1 in advance and correcting carry, which reduces the resource consumption of the modulo (2n-2k+1) adder, reduces the required hardware logic and delay, And improve the operation speed.

Description

technical field [0001] The invention belongs to the field of computers and integrated circuits, and in particular relates to the design of a high-speed adder. Background technique [0002] Before introducing the adder, first explain the remainder system (RNS, ResidueNumberSystems). The remainder system RNS is a numerical representation system that describes numbers through the remainder of a set of pairwise coprime remainder bases. by {m 1 ,m 2 ,...,m L} composed of L remainder bases, integer X, 0≤X<M, where M=m 1 ×m 2 ×…×m L , there is a unique expression in the RNS system as X={x 1 ,x 2 ,...,x L}, in Denotes X for modulo m i remainder of . To operate on two operands in the remainder system, the operator is Θ, which can be defined as: [0003] {z 1 ,z 2 ,…,z L}={x 1 ,x 2 ,...,x L}Θ{y 1 ,y 2 ,...,y L},in Here Θ can be modular addition, modular subtraction or modular multiplication. In a remainder system these arithmetic operations are performed...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the invention is in order to solve the existing mold-oriented (2 n -2 k +1) The problem of the resource consumption of the adder and the low speed, a modulo (2 n -2 k +1) adder

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