Method for producing stressed semiconductor wafers and devices comprising same
A technology of stressed crystalline layer and semiconductor, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc.
Inactive Publication Date: 2016-03-02
GLOBALFOUNDRIES INC
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Problems solved by technology
While using a global approach to stress introduction generally results in stronger and more uniform stress compared to a local approach, using a local approach to stress introduction into a semiconductor wafer is generally favored due to its ease of integration within the device formation method
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[0017] The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description.
[0018] Provided herein are methods for fabricating stressed semiconductor wafers and for fabricating devices comprising stressed semiconductor wafers. Method for producing a stressed semiconductor wafer By etching a first via through a stressed crystalline layer By selectively releasing stress in the stressed crystalline layer By transferring stress from a pseudomorphic formed stressed crystalline layer to a semiconductor wafer And the biaxial stress is introduced into the semiconductor wafer. The first via is also at least partially etched through into the semiconductor wafer and the first via in the semiconductor wafer is then filled with a filling material that prevents the str...
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Abstract
The present invention provides methods of making stressed semiconductor wafers and devices comprising the same. An exemplary method for preparing a stressed semiconductor wafer includes providing a semiconductor wafer comprised of a first material having a first lattice constant. A stressed crystalline layer of a second material having a different lattice constant than the first material is pseudomorphically formed on the surface of the semiconductor wafer. A first through hole is etched through the stressed crystalline layer and at least partially penetrates into the semiconductor wafer to relieve the stress of the stressed crystalline layer adjacent to the first through hole, thereby transferring stress to the semiconductor wafer and forming the semiconductor wafer. A stressed area is formed in the circle. The first through hole in the semiconductor wafer is filled with a first filling material to prevent stress dissipation in the semiconductor wafer.
Description
technical field [0001] The present invention generally relates to methods for preparing stressed semiconductor wafers and devices including stressed semiconductor wafers. More particularly, the present invention relates to methods of imparting stress to semiconductor wafers and preparing devices comprising the resulting stressed semiconductor wafers. Background technique [0002] The use of semiconductor wafers as substrates for metal-oxide-semiconductor (MOS) transistors is widely used in electronic devices, such as microprocessors, microcontrollers, and application-specific integrated circuits. MOS transistors generally include a gate electrode formed on a semiconductor wafer, wherein the gate electrode is insulated from the semiconductor wafer by a thin layer of gate insulating material. The source and drain are separated regions with N-type or P-type semiconductor material, and are generally buried in the semiconductor wafer adjacent to both sides of the gate electrode....
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IPC IPC(8): H01L21/02H01L21/336
CPCH01L29/7847
Inventor S·弗莱克豪斯基T·沙伊佩
Owner GLOBALFOUNDRIES INC