Directory storage method, query method and node controller
A node controller and directory technology, applied in the computer field, can solve the problem of large storage resource demand and achieve the effect of reducing the demand
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Embodiment 1
[0086]In Embodiment 1, it is assumed that every 512Bit of data in the DIMM used to expand the memory of the CPU (hereinafter referred to as CPU DIMM) constitutes a Cache Line (that is, equivalent to the data block mentioned above), and each Cache Line is Uniquely corresponds to a storage address of the CPU. In addition, suppose that when the data of the Cache Line is accessed by the remote node, the NC of the CPU node needs to store a corresponding directory in its own storage space to record the data of the Cache Line being cached by the remote node, for example, it needs to record Which remote node caches the data, and whether the remote node exclusively owns the data or shares it with other remote nodes, and so on.
[0087] In the above scenario, in order to solve the problem in the prior art in order to reduce the impact of the insufficient storage space of the NC directory on the use of the data of the remote node cached by the CPU, which will lead to a very large demand ...
Embodiment 2
[0117] Compared with the embodiment 1, the main difference between the embodiment 2 and the embodiment 1 is that the address of the Cache Line and the address of the storage space in the NCDIMM are mapped differently.
[0118] Specifically, the mapping manner between the address of the Cache Line in Embodiment 2 and the address of the storage space in the NC DIMM is as follows Figure 12 shown. For such as Figure 12 The description of the mapping relationship shown is the same as that of the previous Figure 4 The description of the shown mapping relationship is similar and will not be repeated here.
[0119] Depend on Figure 12 It can be seen from the shown mapping relationship that in Embodiment 2, the number of bits of Mux is 2. In this way, what each storage space set addressed according to Index and Mux in embodiment 2 includes 4 storage spaces, wherein, each storage space is divided into 8 storage subspaces, such as Figure 13 shown.
[0120] In embodiment 2, if ...
Embodiment 3
[0122] Compared with Embodiment 1 and Embodiment 2, the main difference between Embodiment 3 and Embodiment 1 and Embodiment 2 is that the address of the Cache Line and the address of the storage space in the NC DIMM are mapped differently.
[0123] Specifically, the address of the Cache Line in Embodiment 3 is mapped to the address of the storage space in the NC DIMM as follows Figure 14 shown. for Figure 14 The description of the mapping relationship shown is the same as that of the previous Figure 4 with Figure 12 The description of the shown mapping relationship is similar and will not be repeated here.
[0124] Depend on Figure 14 From the mapping relationship shown, it can be seen that in Embodiment 3, no content is selected from the address of the Cache Line as the Mux. In this way, each set of storage spaces addressed according to Index and Mux in Embodiment 3 includes one storage space, where each storage space is divided into 32 storage subspaces.
[0125]...
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