A fractional frequency division circuit and method based on a programmable continuously variable mode frequency divider

Abstract

The present invention proposes a fractional frequency division circuit based on a programmable continuously variable modulus frequency divider, comprising: an FPGA circuit and a programmable continuously variable modulus frequency divider; the FPGA circuit is provided with a Σ-Δ modulator to generate modulation signal, through the mode line to control the programmable continuous variable mode frequency divider to change the frequency division ratio; the programmable continuous variable mode frequency divider divides the input signal, and the output signal is divided into two channels, one of which is used as a fractional frequency divider The output signal is input to the FPGA circuit as the control clock of the Σ-Δ modulator. The fractional frequency division circuit based on the programmable continuous modulus frequency divider of the present invention can perform fractional frequency division on the DC-14GHz input signal, and the output signal frequency can reach up to 270MHz, which can be realized by using an ordinary FPGA circuit and is used for decimal lock. In the phase loop, the phase detection frequency can be greatly increased, thereby improving the phase noise of the fractional phase-locked loop output.

Description

technical field [0001] The invention relates to the technical field of testing, in particular to a fractional frequency division circuit and a fractional frequency division method. Background technique [0002] With the development of microwave technology, the requirements for the phase noise of microwave test signals are getting higher and higher, and there is an urgent need to study low-noise frequency synthesis technology, and phase-locked loop is one of the main methods of frequency synthesis at present. An effective way to improve the phase noise of the PLL output is to increase the phase detection frequency. Increasing the phase detection frequency means increasing the input signal frequency of the fractional frequency division circuit, which requires the fractional frequency division circuit to perform fractional frequency division processing on high-frequency signals. [0003] figure 1 Shown is the schematic diagram of the existing fractional frequency division circ...

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Problems solved by technology

[0005] The present invention proposes a fractional frequency division circuit and method based on a programmable continuous modulus frequency divider, which solves the problem that a high-speed FPGA circuit is required when the existing fractional frequency division circuit is used in a high-discrimination phase-locked loop

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