High reduction degree spatial domain image zooming method based on FPGA platform
A technology of image scaling and spatial domain, which is applied in the field of image processing and can solve the problems of video streams or images that are difficult to meet the requirements of clarity and detail.
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[0014] The FPGA platform-based high-reducibility spatial domain image scaling method of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. The following examples are only used to illustrate the present invention but not to limit the present invention.
[0015] The high-reducibility spatial domain image scaling method based on the FPGA (Field Programmable Gate Arrays) platform of the present invention, the software used in the method includes a pixel information buffer module clock adjustment module, a neighboring related pixel extraction module, a bilinear Coefficient statistics module and output value calculation module, such as figure 2 As shown, the specific steps of the method are as follows:
[0016] The pixel information cache module and the clock adjustment module calculate the number of pixels that need to be cached according to the video scaling ratio, and use RAM resources to cache, and adju...
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