FPGA global clock detection technique for manned spacecraft

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) global clock detection technique for a manned spacecraft. The FPGA global clock detection circuit comprises a global clock frequency dividing circuit, a first synchronization circuit, a second synchronization circuit, a NOT gate and an XOR gate with two input terminals, wherein the global clock frequency dividing circuit is used for frequency division of the global clock to generate a frequency division clock signal; the input terminal of the first synchronization circuit synchronizes the frequency division clock signal to enable a detection clock signal and the frequency division clock signal to be synchronous, and under the control of the detection clock signal and based on the frequency division clock signal, a first detection signal is generated; the input terminal of the NOT gate is connected with the output terminal of the frequency dividing circuit and conducts NOT operation on the frequency division clock signal; the second synchronization circuit is connected with the output terminal of the NOT gate, and under the control of the detection clock signal and based on the calculation result of the frequency division clock signal by the NOT gate, a second detection signal is generated; the XOR gate conducts XOR operation on the first detection signal and the second detection signal. The FPGA global clock detection technique for the manned spacecraft can judge whether the global clock fails to work according to the output of the XOR gate.

Description

technical field [0001] The invention relates to a clock detection technology, in particular to an FPGA global clock detection technology. The invention is a manned spacecraft FPGA global clock detection circuit. Background technique [0002] The use of FPGA in manned spacecraft has become more and more common, and the reliability and safety design has been reflected in more and more manned spacecraft. The global clock is a prerequisite for the normal operation of the FPGA. The global clock controls the entire working state and the corresponding output state of the FPGA. Therefore, the validity detection of the global clock is very important for the FPGA, especially in the field of aerospace. The detection of the FPGA global clock is very important for aerospace. Device safety plays a very important role. [0003] The global clock detection can output a fault signal according to the validity of the global clock, and reset the circuit and output the signal according to the fa...

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is that the prior art cannot detect the validity of the global clock

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