35results about How to "Fast response to faults" patented technology

The invention discloses an energy management and control emergency plan processing method based on graphic modeling, which comprises the following steps: using graphic programming to compile an operation plan, describing the operation plan in the form of a plan flow chart; saving the operation plan into a plan library, and Establish the corresponding relationship between the operation plan and the meta-event in the event pool of the plan library; listen to the event pool, query the event pool when an event occurs, and list possible operation plans that meet the conditions through event retrieval and adaptation, providing operators with Corresponding plan flow chart, after confirming that the operation plan is correct, the operator can choose to automatically execute the operation plan or manually execute the operation plan step by step. The present invention compiles the experience of enterprise failure emergency treatment into a plan in the form of a plan flow chart through graphic programming, and uses automatic control means to automatically execute the plan when a fault occurs or the trigger condition of the plan is met, so as to realize fast execution operation and accurate recovery of faults the goal of.

The invention discloses a hybrid power switch and its application in a flexible direct current transmission converter. The hybrid power switch is composed of a fast-isolated mechanical switch and a bidirectional power electronic switch connected in series and connected in parallel with a power electronic switch with an anti-parallel diode. Composed of switches, it has the advantages of low conduction loss of mechanical switches and good switching characteristics of power electronic devices. The sub-modules that the hybrid power switch can be applied to include but are not limited to full-bridge sub-modules, self-resistance sub-modules, half-bridge and full-bridge hybrid sub-modules, twin-clamp sub-modules, interleaved sub-modules and the above-mentioned sub-modules. A mix of modules with other submodules that do not have fault handling capabilities. The MMC topology containing hybrid switches can limit the DC short-circuit current by blocking sub-modules or generating negative levels, reducing the requirements of the DC power grid on the response speed and breaking capacity of the DC circuit breaker, thereby reducing the manufacturing difficulty and production cost of the DC circuit breaker.

The invention provides a master-slave synergic control method and control system of a DC circuit breaker. The method comprises the steps of switching off a mechanical branch switch and recording faultgeneration time when a fault occurs and a breaking signal is given out from a slave control signal; breaking the mechanical switch when the fault generation time is smaller than a time threshold anda current is detected to be 0; and receiving a master control signal when the fault generation time is not smaller than the time threshold and that the mechanical switch is switched off to reach voltage resistance is detected, and judging whether a main branch switch of the DC circuit breaker is switched off or not according to the received master control signal, wherein the master control signalis a system detection signal, and the slave control signal is a changing signal of a DC voltage value in the DC circuit breaker. With the technical scheme provided by the invention, the system fault is judged by combining the accuracy of the system detection signal and the rapidness of slave control in the DC circuit breaker, rapid response speed and accurate judgment are achieved, and misoperation of the DC circuit breaker can be effectively prevented.

The invention discloses a temperature sensing optical cable and a preparation method thereof, wherein the temperature sensing optical cable and the preparation method relate to the field of optical communication cables. The temperature sensing cable comprises a cable core, a spiral protective layer and an oversheath, wherein the cable core, the spiral protective layer and the oversheath are successively arranged from inside to outside. The cable core comprises a tight buffer fiber. The cable core further comprises a shape memory alloy wire which is made of a shape memory alloy with a two-way memory effect. The shape memory alloy wire and the tight buffer fiber are arranged in an axial direction and are fixed together. The temperature sensing optical cable can accurately position fault points and furthermore can be recycled. The temperature sensing optical cable has advantages of long service life, high fault response speed, short alarm time, long sensing line length, small dimension and high mechanical performance. Furthermore the temperature sensing optical cable can be widely used in power plant, tunnel, mine and petrochemical project.

The invention discloses a monitoring method and a monitoring system based on the interface and system of the SAP platform; the method includes the following steps: collecting interface data and server system data to be monitored on the SAP platform; configuring monitored points according to the importance level of the monitoring points interface and the monitoring level of the server system; configure the monitoring role user group; configure the role relationship between the monitoring content and the person in charge of monitoring; assign role user groups to each monitoring item; configure the early warning data of each monitoring item: carry out different early warning methods Configure, and configure the frequency of early warning according to the time interval; configure the specific content of monitoring for each monitoring item; store the early warning messages and solutions in the knowledge base; send early warning information according to the monitoring level for the monitored information . The present invention can timely discover the existing or potential problems of the SAP system and peripheral application systems and remind or alarm in real time, so as to ensure that the system has good performance for daily business processing.

The invention discloses a model predictive control method for a doubly-fed wind power generator that does not go off-grid. When the grid voltage drops, the rotor flux linkage predictive control method is adopted, and the optimal voltage vector is selected by predicting the rotor flux linkage to act on the rotor side transformation. The controller realizes the synchronous control of the rotor flux and the stator flux, and weakens the fault impact of the stator flux on the rotor flux, thereby reducing the rotor fault overcurrent. Compared with the model predictive control in the steady state, the control frequency of the rotor flux prediction method used in the grid fault is doubled, the response to the fault is faster, and the rotor current can be effectively controlled by 1.5-1.6 times in the fault state Within the rated current, the electromagnetic torque fluctuation is small, which improves the ability of the doubly-fed wind turbine not to go off-grid during a fault.

The invention provides a high-redundancy synchronization signal switching method for an intelligent rectifier bridge, which includes acquiring three-phase synchronization signals from all rectifier bridges; the synchronization signal driving the trigger pulse comes from the local, and the synchronization signal switching is started immediately after the local synchronization signal fails; The synchronization signal that drives the trigger pulse comes from other smart rectifier bridges, and the local synchronization signal is normal. If the phase deviation of the synchronization signal that drives the trigger pulse exceeds the preset threshold compared with the local same-phase synchronization signal, synchronization signal switching is started; the local three-phase synchronization signal appears fault, and the synchronization signal driving the trigger pulse does not come from the local, select the synchronization signal driving the trigger pulse according to the synchronization signal information provided by the online controller; if the synchronization signal switching is started by the method of step S3, the online acceptance will be suspended within 1 second after the switching. Controller synchronization signal coordination. The invention improves the fault response speed of the high redundancy synchronization scheme and improves the reliability of the system.

The invention relates to an AC short-circuit fault current limiter, comprising: a fast switch, a split reactor, a reactor and a capacitor. Wherein, the split reactor includes a first winding and a second winding whose magnetic flux is reversed. A series resonant circuit composed of a reactor and a capacitor resonates at the power frequency. When the grid is stable, the currents of the branches where the first winding and the second winding are located are equal, the magnetic fluxes cancel, and the current limiter exhibits small impedance or no impedance. After the fault occurs, the short-circuit current contains multiple harmonic components, and the series resonant circuit composed of reactors and capacitors presents impedance, resulting in unequal currents in the branches where the first winding and the second winding are located, increasing the current limiting impedance of the split reactor. , to achieve fast automatic current limiting. Then, the fast switch breaks and extinguishes the arc, which further limits the short-circuit current of the current limiter. The current limiter of the present invention can effectively limit the short-circuit current of the AC power grid and improve the operation reliability of the power grid.

A saturated bridge short-circuit fault current limiter is composed of a saturated reactor and a rectifier bridge. The connection points of the first diode (D1) and the second diode (D2) of the rectifier bridge (Br) are the first AC terminal (A), the third diode (D3) and the fourth diode ( The connection point of D4) is the second AC terminal (B), the connection point of the first diode (D1) and the third diode (D3) is the first DC terminal (M), and the second diode ( The connection point of D2) and the fourth diode (D4) is the second DC terminal (N); the saturable reactor (L) is connected between the first DC terminal (M) and the second DC terminal (N); One end of the AC power supply (Uac) is connected to the first AC terminal (A), and the other end of the AC power supply (Uac) is grounded; one end of the circuit breaker (SW) is connected to the second AC terminal B, and the other end of the circuit breaker (SW) with load (R L ) in series and grounded. Saturable reactors are realized by permanent magnets and DC coils.

The invention discloses an FPGA (Field Programmable Gate Array) global clock detection technique for a manned spacecraft. The FPGA global clock detection circuit comprises a global clock frequency dividing circuit, a first synchronization circuit, a second synchronization circuit, a NOT gate and an XOR gate with two input terminals, wherein the global clock frequency dividing circuit is used for frequency division of the global clock to generate a frequency division clock signal; the input terminal of the first synchronization circuit synchronizes the frequency division clock signal to enable a detection clock signal and the frequency division clock signal to be synchronous, and under the control of the detection clock signal and based on the frequency division clock signal, a first detection signal is generated; the input terminal of the NOT gate is connected with the output terminal of the frequency dividing circuit and conducts NOT operation on the frequency division clock signal; the second synchronization circuit is connected with the output terminal of the NOT gate, and under the control of the detection clock signal and based on the calculation result of the frequency division clock signal by the NOT gate, a second detection signal is generated; the XOR gate conducts XOR operation on the first detection signal and the second detection signal. The FPGA global clock detection technique for the manned spacecraft can judge whether the global clock fails to work according to the output of the XOR gate.