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Power mosfet and its formation method

An integrated circuit and device technology, applied in the field of power MOSFET and its formation, can solve the problems of large gate-drain capacitance change, power MOSFET performance change, large gate-drain overlap, etc.

Active Publication Date: 2016-07-20
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the large process window means that the gate-drain overlap is also large, which in turn has a large gate-to-drain capacitance, and the variation of gate-to-drain capacitance is also large
This leads to performance degradation of the power MOSFET and a large change in the performance of the power MOSFET

Method used

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  • Power mosfet and its formation method
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  • Power mosfet and its formation method

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Embodiment Construction

[0031] The making and using of embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are exemplary, and do not limit the scope of the invention.

[0032] According to various exemplary embodiments, trenched power metal oxide semiconductor field effect transistors (MOSFETs) and methods of forming the same are provided. The intermediate stages of forming a trench power MOSFET are shown. Variations of the embodiments are discussed. Like reference numerals are used to refer to like elements throughout the various drawings and exemplary embodiments.

[0033] Figure 1A to Figure 1J is a cross-sectional view of an intermediate stage in the formation of an n-type trench power MOSFET. refer to Figure 1A , providing a semiconductor region 20 which is part of a semiconductor subst...

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Abstract

A power MOSFET and a forming method thereof are provided. A device comprises a trench extending to a semiconductor region and having a first conductivity, and a conductive field plate located in the trench. A first dielectric layer separates the bottom and the side wall of the field plate from the semiconductor region. A main grid electrode is located in the trench and overlaps the field plate. A second dielectric layer is arranged between the main grid electrode and the field plate and separates the main grid electrode and the field plate from each other. A doped drain electrode (DD) region with a first conductivity is located under the second dielectric layer and has an edge portion overlapping the DD region. A body region comprises a first portion located on the same layer as one part of the main grid electrode and a second portion contacted with the DD region. The body region has a second conductivity opposite to the first conductivity. An MOS-containing device is located on the surface of the semiconductor region.

Description

[0001] Related cross application [0002] This application is a continuation-in-part of US Patent Application Serial No. 13 / 486,681, entitled "Trench Power MOSFET," filed June 1, 2012, which is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates to power MOSFETs and methods of forming them. Background technique [0004] In a conventional split-gate trench power metal-oxide-semiconductor field-effect transistor (MOSFET), the polysilicon gate is divided into upper and lower portions, both formed in the trench. The upper part and the lower part are separated from each other by a dielectric layer. The upper part acts as the main gate for controlling the channel of the power MOSFET and the lower part acts as a field plate for reducing the surface electric field. Therefore, the depth of the main gate depends on the depth of the trench and the thickness of the dielectric layer filled in the groove. Both the depth of the trench...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/423H01L21/336
CPCH01L21/823418H01L21/823456H01L21/823493H01L27/0922
Inventor 伍震威周学良苏柏智柳瑞兴
Owner TAIWAN SEMICON MFG CO LTD