Thread sparing between cores in a multi-threaded processor
A technology of processors and processor controllers, applied in multi-programming devices, electrical digital data processing, fault handling not based on redundancy, etc., capable of solving problems such as damage progress
Active Publication Date: 2014-04-02
IBM CORP
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Problems solved by technology
Such a full core spare may destroy the progress of one or more threads that are executing successfully on the faulty core
Method used
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[0011] Embodiments of systems and methods for thread sparing between cores in a multi-threaded processor are provided through the exemplary embodiments discussed in detail below. Hardware-based thread sparing can be used to transfer a single failed thread from a first core to a second core in a multi-threaded multi-core processor without affecting other threads running on the first core. A thread may be determined to have failed based on a number of recovery attempts occurring during execution of the thread exceeding a recovery attempts threshold. when it is determined that the thread has failed on the first core and the failed thread needs to be transferred, transferring the failed thread's last good architected state from error recovery logic in the first core to the second core, and, Execution of the failed thread may be resumed from its last good architectural state using the resources of the idle thread in the second core. In some embodiments, the resources of the good t...
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The present invention relates generally to error recovery in a multi-threaded processor, and more specifically to a multi-threaded, multi-core processor configured to spare threads between cores. The method includes determining, by a first core of the processor, that a number of recovery attempts made by a first thread on the first core has exceeded a recovery attempt threshold; sending, by the first core to a processor controller in the processor, a request to transfer the first thread to another core of the processor; based on receiving the request, selecting, by the processor controller, a second core from a plurality of cores of the processor to receive the first thread from the first core, wherein the second core is selected based on the second core having an idle thread; transferring a last good architected state of the first thread from an error recovery logic of the first core to the second core; loading the last good architected state of the first thread by the idle thread on the second core; and resuming execution of the first thread on the second core from the last good architected state of the first thread by the idle thread.
Description
technical field [0001] The present invention relates generally to error recovery in multithreaded processors, and more particularly to multithreaded multicore (core) processors configured to spare threads between cores. Background technique [0002] A processor may be configured to execute one thread of instructions at a time, or to execute multiple threads simultaneously. A processor configured to execute multiple threads simultaneously is said to be in simultaneous multithreading (SMT) mode. In SMT mode, hardware resources are shared among multiple software threads executing on the machine. Threads typically exist within a process, and a process may have multiple threads that share a computer resource such as memory. A thread is considered the smallest processing unit that can be scheduled by the operating system. In a multi-core processor that is executing multiple threads, threads can be distributed across multiple cores in the processor, and each core can be configur...
Claims
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IPC IPC(8): G06F15/163G06F9/46
CPCG06F11/2023G06F11/203G06F11/2025G06F11/076G06F9/46G06F11/1658G06F11/0715G06F11/2043G06F11/0724
Inventor F.Y.布萨巴S.R.卡洛C.A.克里格罗夫斯基B.R.普拉斯基岑中龙
Owner IBM CORP