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Techniques and structures for testing integrated circuits in flip-chip assemblies background

一种组合件、组件的技术，应用在电路、电气元件、半导体器件等方向，能够解决IC管芯互连短路、技术不可靠等问题

Inactive Publication Date: 2014-04-02
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, these techniques are not reliable as they can cause shorts between the interconnects of the IC die

Method used

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  • Techniques and structures for testing integrated circuits in flip-chip assemblies background
  • Techniques and structures for testing integrated circuits in flip-chip assemblies background
  • Techniques and structures for testing integrated circuits in flip-chip assemblies background

Examples

Experimental program
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Embodiment Construction

[0019] It can be readily appreciated that components of the invention, such as those generally described herein and shown in the drawings, may be arranged and designed in a variety of different configurations. Accordingly, the following more detailed description of the embodiments of the invention presented in the drawings is not intended to limit the scope of the claimed invention, but is merely representative of some examples of embodiments in accordance with presently contemplated embodiments of the invention. The presently described embodiments will be best understood by referring to the drawings, wherein like parts are designated by like numerals throughout.

[0020] refer to Figures 1A to 1D , shows an embodiment of a process for removing an IC die from an MCM substrate and rebonding the IC die to an SCM substrate. Such as Figure 1A As shown, a multi-chip module (MCM) 100 may include multiple IC dies 102 mounted to a common substrate 104 , such as a multilayer stack-u...

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PUM

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Abstract

A method for rejoining an IC die (102), removed from an existing substrate (104), to a new substrate (106), is disclosed herein. In one embodiment, such a method includes grinding an existing substrate (104) from an IC die (102) to create a substantially planar surface exposing interconnect (202) and surrounding underfill material (204). A new substrate (106) is provided having electrically conductive pedestals (300) protruding therefrom. The electrically conductive pedestals (300) are positioned to align with the exposed interconnects (202) and have a melting point substantially higher than the melting point of the interconnect (202). The method places the exposed interconnect (202) in contact with the electrically conductive pedestals (300). The method then applies a reflow process to melt and electrically join the exposed interconnect (202) with the electrically conductive pedestals (300). A structure produced by the method is also disclosed.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly, to techniques and structures for testing integrated circuits in flip chip assemblies. Background technique [0002] Failure analysis is the process of determining the cause of a failure, collecting and analyzing failure-related data, and drawing conclusions to eliminate or mitigate the cause of the failure. In the semiconductor industry, failure analysis of integrated circuits is essential to improve the quality and design of integrated circuits and the manufacturing process used to produce integrated circuits. Manufacturers of integrated circuits need to be aware of the vulnerabilities of their circuits and fabrication processes in order to develop means for monitoring and eliminating such vulnerabilities. [0003] Failure analysis of integrated circuits can be challenging due to the inclusion of such integrated circuits into a variety of different electronic packages. Fo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/00
CPCH01L24/13H01L2224/81411H01L21/563H01L2224/05571H01L2224/81192H01L2224/05616H01L2224/81193H01L24/05H01L23/49811H01L2224/05573H01L2224/05611H01L2224/81815H01L24/16H01L2224/73104H01L24/81H01L2924/00014H01L2924/00012H01L2924/014H01L2224/0401H01L2924/07802H01L2924/3841H01L2924/00H01L2224/05552
Inventor M·戴斯彻内斯M·高温E·吉谷尔瑞
Owner GLOBALFOUNDRIES INC