Semiconductor device, semiconductor device manufacturing method, and solid-state imaging device
A device manufacturing method and semiconductor technology, which are applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of increasing the circuitous area and hindering the miniaturization of semiconductor devices, and achieve the goal of miniaturization. Effect
Active Publication Date: 2017-06-09
SONY CORP
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- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Therefore, the detour area of wiring for interconnecting elements may be further increased, which may further hinder the miniaturization of semiconductor devices.
Method used
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Examples
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Comparison scheme
Effect test
no. 1 example
[0087] 1. First embodiment (2-layer structure: basic structure (including NAND circuit))
[0088] 1-1 structure
[0089] 1-2 Manufacturing method
[0090] 2. Second Embodiment (Example of Laminated Structure of 3 or More Layers)
[0091] 2-1 Structure
[0092] 2-2 Manufacturing method
no. 3 example
[0093] 3. Third Embodiment (Example of a Laminated Structure Using a Supporting Substrate (Including a NAND Circuit))
[0094] 3-1 Structure
[0095] 3-2 Manufacturing method
no. 4 example
[0096] 4. Fourth Embodiment (Example of Laminated Structure Applied to Solid-State Imaging Device)
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The invention discloses a semiconductor device, a manufacturing method of the semiconductor device and a solid-state imaging device. The semiconductor device includes: a semiconductor layer including an active region; a semiconductor element formed using the active region; connection regions obtained by metallizing some parts of the semiconductor layer in island-like shapes isolated from the active region an insulating film formed to cover one main surface side of the semiconductor layer; electrodes provided to face the semiconductor element and the connection region, and the electrodes are interposed between the semiconductor element and the connection region the insulating film; and contact portions penetrating through the insulating film so as to be selectively formed in desired portions among portions connecting the semiconductor element or the connection region to the electrodes. The present invention can form a desired circuit by selecting the arrangement of the contacts instead of relying only on detours of wiring, and thus can achieve miniaturization of the semiconductor device.
Description
technical field [0001] The present invention relates to semiconductor devices and semiconductor device manufacturing methods, and more particularly, to semiconductor devices in which elements are three-dimensionally arranged by laminating a plurality of semiconductor layers, methods for manufacturing such semiconductor devices, and solid-state imaging using such semiconductor devices device. Background technique [0002] As one of structures configured to achieve higher integration of semiconductor devices, a 3-dimensional structure in which elements having different characteristics are stacked in a plurality of layers has been proposed. In a semiconductor device having such a 3-dimensional structure, for example, there are the following two configurations. [0003] The first configuration is a configuration in which a plurality of substrates in which elements are formed are prepared and bonded to each other. In this case, for example, connection electrodes connected to th...
Claims
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IPC IPC(8): H01L23/528H01L21/768H01L27/146
CPCH01L27/14603H01L27/14612H01L27/14634H01L27/1464H01L27/14687H01L27/1469H01L23/481H01L27/14614H01L27/14636H01L27/14643H01L27/14689H01L2224/08137H01L2224/16145H01L2224/8034H01L2224/80357H01L2224/80895H01L2224/80896Y02E10/547Y10S977/742Y10S977/954B82Y20/00H01L31/0224H01L31/028H01L31/18
Inventor 横山孝司
Owner SONY CORP