Semiconductor package and method of fabricating same

Abstract

A semiconductor package and a method of fabricating the same are provided. The semiconductor package includes an encapsulant having a top surface and a bottom surface opposite to the top surface; a semiconductor chip embedded in the encapsulant having an active surface, an inactive surface opposite to the active surface, and lateral surfaces interconnecting the active surface and the inactive surface, wherein the active surface protrudes from the bottom surface of the encapsulant and the semiconductor chip further has a plurality of electrode pads disposed on the active surface; a positioning member layer formed on a portion of the bottom surface of the encapsulant, covering the lateral surfaces of the semiconductor chip that protrude therefrom, and exposing the active surface; and a build-up trace structure disposed on the active surface of the semiconductor chip and the positioning member layer formed on the bottom surface of the encapsulant. Deviation of the semiconductor during package molding is prevented, and thus alignment precision of subsequent processes is effectively enhanced and the product yield is thus improved.

Description

technical field [0001] The invention relates to a semiconductor package and a manufacturing method thereof, in particular to a package capable of solving wafer-level semiconductor packaging crystal grain offset and a manufacturing method thereof. Background technique [0002] With the evolution of semiconductor technology, semiconductor products have developed different packaging product types. In order to pursue the lightness, thinness and shortness of semiconductor packages, a method that can provide more sufficient surface area to carry more input / output terminals ( I / O) or solder ball wafer level packaging (Wafer Level Chip Scale Package, WL-CSP), and can form a circuit redistribution layer on the semiconductor chip, and use the redistribution layer (redistribution layer, RDL) technology to reconfigure the chip on the solder pad to the desired position. [0003] However, in the manufacturing method of this package, in order to simplify the processing steps and improve t...

AI Technical Summary

Problems solved by technology

However, if Figure 1D As shown on the left, the laminated adhesive film 12 after pressing and heating by the pressing machine will produce fluidity, impact the semiconductor chip 11 to make it displace, and the offset exceeds the original predetermined position A, so that the conductive blind hole 150 cannot be effectively electrically connected. Connect the electrode pad 110 and the circuit layer 152, resulting in a decrease in product yield

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