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Ways to Reduce Parasitic Mismatches

A resistor-layout technique used in the field of correcting resistance ratio mismatches between pre-layout simulation results and post-layout test results, addressing timing, noise and reliability effects, ratio changes, etc.

Active Publication Date: 2017-06-16
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These changes can cause changes in the ratio between the two semiconductor resistors
As such, key performance metrics such as timing, noise, and reliability may be adversely affected

Method used

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  • Ways to Reduce Parasitic Mismatches
  • Ways to Reduce Parasitic Mismatches
  • Ways to Reduce Parasitic Mismatches

Examples

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Embodiment Construction

[0038] The making and using of preferred embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0039] The present invention will be described with reference to preferred embodiments in a specific context, namely a method of correcting a resistance ratio mismatch between pre-layout simulation results and post-layout test results. However, the present invention can also be applied to correct mismatches caused by various parasitic elements in various semiconductor devices. Various embodiments will be described in detail below with reference to the accompanying drawings.

[0040] figure 1 A flowchart comprising a series of steps for correcting a mismatch be...

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PUM

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Abstract

A method for reducing parasitic mismatch, comprising utilizing a first simulation tool to generate a first netlist file by a first layout through a resistance-inductance-capacitance (RLC) extraction mechanism, implementing a V / I test to the network by a second simulation tool, Whether there is a mismatch is determined based on the results of the V / I test, and the connection traces of the net are modified to generate a second layout.

Description

technical field [0001] The present invention relates to a method of correcting a resistance ratio mismatch between pre-layout simulation results and post-layout test results. More specifically, the present invention relates to correcting mismatches caused by various parasitic elements in various semiconductor devices. Background technique [0002] With the development of semiconductor technology, integrated circuits (ICs) have tended towards small feature sizes, such as 65nm, 45nm, 32nm and below. Semiconductor technologies with small feature sizes lead to more interaction between semiconductor manufacturing and design. For example, for devices with small feature sizes, the impact of parasitic effects will become more important. IC designers can implement a variety of simulation and optimization programs to ensure that devices with small feature sizes meet their specified performance specifications. [0003] Semiconductor resistors are widely used in integrated circuits. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F30/398G06F30/394
Inventor 黄超明李惠宇
Owner TAIWAN SEMICON MFG CO LTD