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Method for unwinding buses in system in package under bilateral multi-bypass constraint

A system-level packaging and bus technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as signal confusion

Inactive Publication Date: 2014-06-25
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The signal sequence of the chips in the chip interconnection is also a factor that cannot be ignored in the design of interconnection tools. Since the chips are manufactured by different manufacturers, the sequence of the connection signals between them may not be exactly the same. Simply press the relative Possibility of signal confusion due to positional relational interconnection

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  • Method for unwinding buses in system in package under bilateral multi-bypass constraint
  • Method for unwinding buses in system in package under bilateral multi-bypass constraint
  • Method for unwinding buses in system in package under bilateral multi-bypass constraint

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Embodiment Construction

[0057] The present invention can be aimed at any two chip bus interconnection situations. After renaming the two bus signals that need to be interconnected, start with a x Represents the first unconnected bus signal on the top left, denoted by b y Represents the first unconnected bus signal on the left at the bottom, and u represents the number of all unconnected network lines; the calculation is the same as a x connected b ax The number of bus signals p that are not connected on the left, calculated with by connected a by The number of unconnected bus signals q on the left side of , select the connection mode based on the size relationship of p, q, u. The following is a practical example to illustrate the bilateral multiple detour method: After renaming the bus signals, the top bus signal sequence is (19, 17, 2, 11, 10, 15, 16, 1, 8, 4, 5, 20, 7, 12, 18, 14, 9, 13, 6, 3), the iterative process is as follows:

[0058] For the first iteration, x=1, y=1, p=19, q=8, u=20.u>p...

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Abstract

A method for unwinding buses in a system in a package under the bilateral multi-bypass constraint is characterized in that an appropriate mode is selected from predefined connecting modes to make connecting lines in the buses interconnected in the left to right bus signal sequence, an optimal mode is utilized to replace an original connecting mode under the feasible condition through later period detection, and then interconnection unwinding is achieved through fewer bypasses.

Description

technical field [0001] The invention relates to an unwinding method of a bus under the constraints of bilateral multiple detours in a system-in-package, which belongs to the field of chip bus signal interconnection design in the field of integrated circuit computer aided design. Background technique [0002] In the current VLSI design, as the scale becomes larger and larger, designers need to interconnect more and more chips under more and stricter physical constraints. The traditional manual method due to the increase in scale has already Not suitable for the development of the industry. It is necessary to design a chip interconnection tool that can automatically realize and guarantee under certain conditions, such as length matching and signal pair constraints. The signal order of the chips in the chip interconnection is also a factor that cannot be ignored in the design of interconnection tools. Since the chips are manufactured by different manufacturers, the order of th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 董社勤林涛罗辅其
Owner TSINGHUA UNIV