Unlock instant, AI-driven research and patent intelligence for your innovation.

Fan-out wafer-level packaging structure and manufacturing technology

A technology of wafer-level packaging and manufacturing process, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as difficulties and achieve the effect of improving warpage

Inactive Publication Date: 2014-07-02
NAT CENT FOR ADVANCED PACKAGING
View PDF3 Cites 12 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, it is very difficult to control the warpage of the fan-out package using the molding process, and it is also difficult to control the slippage and shift caused by the expansion and contraction of the molding compound (EMC).

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Fan-out wafer-level packaging structure and manufacturing technology
  • Fan-out wafer-level packaging structure and manufacturing technology
  • Fan-out wafer-level packaging structure and manufacturing technology

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0031] The present invention will be further described below in conjunction with specific drawings.

[0032] Such as Figure 11 , Figure 12 As shown: the fan-out wafer level packaging structure includes a chip 100 with a first metal electrode 102a and a second metal electrode 102b and a metal layer 203, and the chip 100 and the metal layer 203 are molded into a whole by a plastic packaging material 501, And the front side 100a of the chip 100 and a surface 203a of the metal layer 203 are located on the same plane as the front side 501a of the molding material 501; a dielectric layer 901 is arranged on the front side 501a of the molding material 501, and the rewiring metal is arranged in the dielectric layer 901. The wiring layer 1101 and the UBM layer 1201, the solder ball 1301 is placed on the UBM layer 1201, and then the metal wiring layer 1101 is connected to the first metal electrode 102a, the second metal electrode 102b and the UBM layer 1201.

[0033] The manufacturi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a fan-out wafer-level packaging structure and a manufacturing technology. The manufacturing technology of the fan-out wafer-level packaging structure is characterized in that when the fan-out wafer-level packaging structure is manufactured, the technological process that the front faces of chips face downwards is adopted, a metal layer is manufactured on a carrier wafer, and then through holes are formed according to the arrangement positions of the chips, or a metal layer with through holes directly formed is bonded to the carrier wafer; the chips are attached into slots of the metal layer with the front faces downwards, and then the packaging technology is performed. Thus, the internal structure of fan-out wafer-level packaging is changed, the rigidity and the thermal expansion coefficient of the packaging structure are enhanced, and then warpage and slippage and shift caused by expansion and contraction of EMC of the whole wafer can be controlled. Moreover, the metal material can have better thermal conduction and electromagnetic shielding effects.

Description

technical field [0001] The invention relates to a fan-out wafer-level packaging structure and a manufacturing process, belonging to the technical field of semiconductor packaging. Background technique [0002] Fan-out wafer-level packaging is an embedded package processed at the wafer level, and it is also one of the main advanced packages with a large number of I / Os and good integration flexibility. Fan-out wafer-level packaging technology generally uses individual microchips cut from a wafer and then embedded on a new "artificial" wafer. When embedding, there must be sufficient spacing between microchips for fan-out rerouting. At present, it is very difficult to control the warpage of the fan-out package using the molding process, and it is also difficult to control the slippage and shift caused by the expansion and contraction of the molding compound (EMC). Contents of the invention [0003] The purpose of the present invention is to overcome the deficiencies in the p...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L23/31H01L21/98
CPCH01L21/568H01L2224/04105H01L2224/12105H01L2924/3025H01L2924/3511
Inventor 王宏杰陈南南
Owner NAT CENT FOR ADVANCED PACKAGING