A shift register unit, gate driving device and display panel
A shift register and gate technology, applied in static memory, digital memory information, instruments, etc., can solve problems such as signal distortion of shift register units, and achieve the goal of solving signal distortion, reducing leakage current, and reducing the influence of leakage current. Effect
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Embodiment 1
[0034] Embodiment 1, taking each transistor as an example of a PMOS transistor for illustration, is as follows:
[0035] see figure 2 The first shift register unit provided by the embodiment of the present invention includes: a first transistor M1, the gate of which is electrically connected to the first clock signal terminal CK1, and the first pole thereof is used as the input terminal IN of the shift register unit, and The second pole is electrically connected to the first end of the capacitor C1, and the second end of the capacitor C1 is the output end OUT of the shift register unit;
[0036] The gate of the second transistor M2 is electrically connected to the second clock signal terminal CK2, its first pole is electrically connected to the second pole of the first transistor M1, and its second pole is electrically connected to the first pole of the third transistor M3;
[0037] The gate of the third transistor M3 is electrically connected to the first level signal termi...
Embodiment 2
[0069] Embodiment two, provide such as Figure 5 and Figure 7 The shift register unit shown is the same as that of the first embodiment figure 2 and Figure 4The shift register cell shown has the same element structure, but Figure 5 and Figure 7 Each transistor in the shown shift register unit is an NMOS transistor, the first pole of each NMOS transistor is a source, and the second pole is a drain. The details are as follows:
[0070] against Figure 5 and Figure 7 The shift register cell shown, provides Figure 6 The timing diagram of the operation is shown. see Figure 5 , this embodiment provides a schematic structural diagram of the third type of shift register unit. The input terminal IN of the shift register unit is connected to the monostable pulse signal STV, and the monostable pulse signal STV is active at high level; the first clock signal terminal CK1 is connected to the second clock signal CKB, and the second clock signal terminal CK2 The first cloc...
Embodiment 3
[0095] Embodiment three, provide such as Figure 8 and Figure 10 In the shift register unit shown, each transistor is an NMOS transistor. Figure 8 and Figure 10 The shift register unit shown is slightly different from the shift register unit provided in Embodiment 1 or Embodiment 2, and the details are as follows:
[0096] see Figure 8 , the embodiment of the present invention provides a fifth shift register unit, including: the gate of the first transistor M1 is electrically connected to the first clock signal terminal CK1, and its first pole is used as the input terminal IN of the shift register unit, and its second The pole is electrically connected to the first end of the capacitor C1, and the second end of the capacitor C1 is the output end OUT of the shift register unit;
[0097] The gate of the second transistor M2 is electrically connected to the second clock signal terminal CK2, its first pole is electrically connected to the second pole of the first transisto...
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