A three-port floating-point register file for risc processors

A technology of register files and registers, applied in the direction of machine execution devices, etc., can solve the problems of increasing the complexity of processor design and the difficulty of back-end wiring, waste of hardware resources, increasing design power consumption, etc., to solve the problem of SRAM bandwidth, Simple control and low power consumption

Active Publication Date: 2016-07-06
NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The semi-custom design based on the cell library mainly has the following shortcomings: (1) hardware resources are wasted, which increases the power consumption of the design
Since this method is based on the SRAM in the cell library, there may not be a suitable size of SRAM, resulting in greater waste of resources and increased power consumption. In addition, the design requires the processor to generate 8 sets of control signals, which increases the complexity of the processor design and the subsequent Difficulty of terminal wiring

Method used

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  • A three-port floating-point register file for risc processors
  • A three-port floating-point register file for risc processors
  • A three-port floating-point register file for risc processors

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Embodiment Construction

[0043] The patent of the present invention will be described in further detail below in conjunction with the accompanying drawings, which is an explanation of the present invention rather than a limitation.

[0044] Such as figure 2 , image 3 As shown, a three-port floating-point register file for RISC processors includes a write address decoding module, a write control module, a write data interconnection network, a register array, a first read address decode module, and a second read address decode module. Code module, first read control module, second read control module, read data interconnection network;

[0045] The write address decoding module, the input is register file write enable and write address, when the write enable is valid (high level), the write enable w_en of the register AR corresponding to the write address is valid, and it is output To the Write Control Module and to the Write Data Interconnect Network.

[0046] The output of the write control modul...

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Abstract

The invention discloses a three-port floating point register file orienting an RISC (reduced instruction set computer) processor. Precision zone bits of a source operand and a target operand are added into an input signal of a register file, the control logic of a register array simultaneously performs read-write operation on the register designated by the address of the source operand and the target operand and the registers of which the addresses are adjacent to the that of the register according to the precision zone bits and the read-write zone bits, the read and write back of dual-precision of four-precision floating point number can be finished in one single period and the SRAM (static random access memory) bandwidth problem in the floating point operation is solved.

Description

technical field [0001] The patent of the invention belongs to the field of microprocessor architecture, and relates to a three-port floating-point register file oriented to RISC processors. Background technique [0002] Most of the instruction operations of the RISC processor are carried out between registers, and the read and write operations of the external memory must be completed by special memory access instructions. In order to speed up the execution of instructions, the RISC processor has a register file inside. During the execution of the instruction, the source operand is obtained from the register file, and the execution result (target operand) is written back to the register file. In general, an instruction of a RISC processor uses two source operands to calculate a target operand. Based on this, the register file should have three ports, including two read ports and one write port. [0003] At present, there are two main design methods for three-port register fi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
Inventor 陈庆宇吴龙胜段青亚盛廷义唐威
Owner NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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