Array substrate, display device and detection method thereof
A technology for display devices and array substrates, applied to static indicators, instruments, etc., can solve problems such as difficult to apply process control and poor analysis, and achieve the effect of rapid judgment
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Embodiment 1
[0031] figure 2 It is a schematic diagram of the terminals of the array substrate in the first embodiment of the present invention. The present invention provides an array substrate, comprising: a substrate, including a display area and a non-display area, a plurality of terminal areas protrude from the non-display area, and the plurality of terminal areas are used for crimping a flexible display circuit board (see figure 1 ). Such as figure 2 As shown, each terminal area is roughly divided into a first sub-terminal area 21, a second sub-terminal area 22, a third sub-terminal area 23, and an alignment mark area 24, and the first and third terminal areas 21, 23 are distributed on both sides of the second sub-terminal area 22 . For example, the first and third sub-terminal areas 21 and 23 located at both ends are WOA (wire on array) terminals (such as VGL, VGH, Vcom, etc.), and the second sub-terminal area 22 is an Output output terminal connected to the data voltage (such...
Embodiment 2
[0040] Figure 6 It is a schematic diagram of the terminals of the array substrate according to the second embodiment of the present invention. Such as Figure 6 As shown, the first sub-terminal area 61 and the third area 63 are WOA terminal areas, and the second sub-terminal area 62 is an output terminal area for connecting data voltages. Wherein, the area outside the first sub-terminal area 61 and the area outside the third sub-terminal area 63 are respectively provided with an area 65 and an area 66. Optionally, a non-signal terminal Dummy is provided outside the areas 65 and 66, and both use semiconductor Conductive materials such as ITO are patterned.
[0041] Figure 7 for the invention Figure 6 A partially enlarged schematic diagram of the terminal area 65 of the middle array substrate. Such as Figure 7 As shown, the area 65 includes a terminal Dummy, a terminal Vcom, a terminal VGH, a terminal VGH, and a terminal OE. That is, a non-signal terminal Dummy is pro...
Embodiment 3
[0045] Figure 10 It is a partially enlarged schematic diagram of the terminals of the array substrate according to the third embodiment of the present invention. Such as Figure 10 As shown, the first non-signal terminal Dummy is electrically connected to the surface-covered semiconductor conductive material 1061 of the second Vcom terminal, and the third non-signal terminal Dummy is connected to the fourth VGH terminal through the first metal layer 1062, preferably , covering the ITO layer pattern 36 on both ends of the non-signal terminal Dummy and adjacent terminals, thereby saving material and avoiding short circuits between adjacent signal terminals.
[0046] Figure 11 for the invention Figure 10 Schematic diagram of the cross-section of the terminals of the array substrate. The top is a flexible circuit board, the middle is an anisotropic conductive film (not shown) containing conductive particles, and the bottom is an array terminal. The flexible circuit board i...
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