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Conductive line patterning

A patterning, wire technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of layout method lithography process limitations and so on

Active Publication Date: 2014-12-31
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In some layouts, cut poly (CPO) patterns are used to cut conductive lines such as polysilicon lines, but as integrated circuits shrink in size, some layout methods are limited by photolithography processes

Method used

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  • Conductive line patterning
  • Conductive line patterning
  • Conductive line patterning

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Embodiment Construction

[0027] The making and using of various embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0028] Furthermore, the present invention may repeat reference numerals and / or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the different embodiments and / or arrangements discussed. In addition, in the present invention, a component formed on, connected to and / or coupled to another component may include an embodiment in which the two components are formed in direct contact, and may also include an embodiment in which an additional component may be formed on two co...

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PUM

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Abstract

A method includes placing two conductive lines in a layout. Two cut lines are placed over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.The invention provides a line structure and a computer readable medium.

Description

technical field [0001] The present invention relates generally to the field of integrated circuits and, more particularly, to patterning of conductive lines. Background technique [0002] For integrated circuit layout, there are dimensional constraints such as minimum pitch or spacing. In some layouts, cut poly (CPO) patterns are used to cut conductive lines such as polysilicon lines, but some layout methods are limited by the photolithography process as the size of integrated circuits shrinks. It would be desirable to provide methods that overcome the shortcomings of the current state of the art. Contents of the invention [0003] According to one aspect of the present invention, there is provided a method comprising: placing two molded wires in a layout; placing two cut lines over at least a portion of the two molded wires in the layout, the cut lines specifying two directing cut portions of the wires, and the cut lines are isolated from each other within the constrain...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50H01L27/02
CPCG06F30/394H01L21/32139H01L23/522H01L27/0207H01L2027/11875H01L2924/0002H01L2924/00H01L21/0274H01L21/76816H01L21/76877H01L21/76892H01L23/5226H01L23/528H01L23/53209H01L23/53271
Inventor 刘如淦谢东衡蔡宗杰吴俊毅李亮峣丁至刚
Owner TAIWAN SEMICON MFG CO LTD