Unlock instant, AI-driven research and patent intelligence for your innovation.

A high-voltage ESD protection circuit with stacked scr‑ldmos

An ESD protection and high-voltage technology, applied in the field of electronics, can solve the problems of effectively protecting the internal working circuit and increasing the breakdown voltage, reducing the risk of latch-up effect, increasing the maintenance voltage, and solving the problem that the maintenance voltage is too low. Effect

Active Publication Date: 2017-05-10
UNIV OF ELECTRONICS SCI & TECH OF CHINA
View PDF3 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this stack structure can increase the sustaining voltage, it also increases the breakdown voltage. If the breakdown voltage is too high, the purpose of effectively protecting the internal working circuit cannot be achieved.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A high-voltage ESD protection circuit with stacked scr‑ldmos
  • A high-voltage ESD protection circuit with stacked scr‑ldmos
  • A high-voltage ESD protection circuit with stacked scr‑ldmos

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] image 3 The structure schematic diagram of the NLDMOS trigger stacked SCR-LDMOS high-voltage ESD protection circuit provided for this embodiment includes a P-type substrate 201, a first high-voltage N-type well region 202, a second high-voltage N-type well region 203, and a third high-voltage N-type well region. type well region 204, the first P type well region 205, the second P type well region 206, the third P type well region 207, the first P type heavily doped region 208, the second P type heavily doped region 211, the second P type well region Three P-type heavily doped regions 212, fourth P-type heavily doped regions 214, fifth P-type heavily doped regions 216, sixth P-type heavily doped regions 217, seventh P-type heavily doped regions 219, Eight P-type heavily doped regions 221, ninth P-type heavily doped regions 222, first N-type heavily doped regions 209, second N-type heavily doped regions 210, third N-type heavily doped regions 213, Four N-type heavily do...

Embodiment 2

[0043] Such as Figure 5 As shown, in embodiment 2, on the basis of embodiment 1, PLDMOS is used instead of NLDMOS. At this time, the other end of the resistor 232 connected to the gate of PLDMOS is connected to the anode of SCR-LDMOS1, and the rest of the connections are the same as that of NLDMOS. The working principle of this embodiment is the same as that of Embodiment 1.

[0044] Embodiment 2 uses PLDMOS instead of NLDMOS to trigger the stacked SCR-LDMOS structure, because PLDMOS has a higher sustain voltage, which makes the sustain voltage after the first snapback higher, which also helps to resist noise.

[0045] Figure 6 The equivalent circuit diagram of the high-voltage ESD protection circuit of the LDMOS trigger stacked SCR-LDMOS provided by the present invention. The present invention can greatly increase the sustain voltage by stacking more SCR-LDMOS stacked units 501, and more effectively prevent the occurrence of the latch-up effect.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a high-voltage ESD protection circuit of stacked SCR-LDMOS, which belongs to the field of electronic technology. Including 1 NLDMOS, 1 resistor 232 and N SCR-LDMOS stacked units, the SCR-LDMOS stacked unit includes an SCR-LDMOS device and a trigger resistor, where N≥2, and (N+2 ) a P-type heavily doped region is grounded as a guard ring. The circuit triggers the stacked SCR-LDMOS through the breakdown of the LDMOS. While the trigger voltage is not increased, the stacked SCR-LDMOS is used to increase the sustain voltage.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to an electrostatic discharge (ElectroStatic Discharge, referred to as ESD) protection circuit design technology for a semiconductor integrated circuit chip, especially a laterally diffused metal oxide semiconductor field effect transistor LDMOS (Laterally Diffused Metal Oxide Semiconductor, LDMOS for short) triggers the high-voltage ESD protection circuit of stacked SCR-LDMOS (Silicon Controlled Rectifier with LDMOS embedded, SCR-LDMOS for short). Background technique [0002] In the process of chip production, packaging, testing, storage, and handling, electrostatic discharge (ElectroStatic Discharge, referred to as ESD) is an inevitable natural phenomenon that is ubiquitous. With the reduction of the feature size of integrated circuit technology and the development of various advanced technologies, it is more and more common for chips to be damaged by ESD phenomen...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H02H9/04
Inventor 乔明马金荣张晓菲甘志张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA