Laterally diffused metal oxide semiconductor (LDMOS) transistor, layout method and manufacture method

Abstract

The invention provides a structure of a laterally diffused metal oxide semiconductor (LDMOS) transistor, a manufacture method and a layout method of the structure. The structure comprises a substrate, a first mixing pit, a second mixing pit, a grid electrode structure, a first isolation structure, a second isolation structure, a source region, a drain region, an interlamination medium layer, a source region plug and a drain region plug. The first mixing pit and the second mixing pit are located in the substrate, the grid electrode structure is located above the first mixing pit and the second mixing pit, the isolation structure surrounds the first mixing pit and the second mixing pit, one side of the second isolation structure is adjacent to the grid electrode structure, the second isolation structure has two opposite ends and is connected with the first isolation structure, the source region is located in the first mixing pit, a third isolation structure is formed in the source region, and the source region is used for increasing resistance of the source region, the drain region is located in the second mixing pit between the first isolation structure and the second isolation structure, and the interlamination medium layer is located on the surface of the substrate, and the source region plug and the drain region plug are located in the interlamination medium layer. The structure guarantees that the LDMOS transistor can be normally opened.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an LDMOS transistor, a layout method thereof, and a manufacturing method of the LDMOS transistor. Background technique [0002] In the development of power integrated circuits, the single-chip process developed to integrate power switches and control circuits, especially the lateral double diffusion MOS (lateral double diffusion MOS, LDMOS) process is a mainstream trend. The LDMOS process is planar diffusion on the surface of the semiconductor substrate to form the main lateral current path. Since LDMOS is manufactured in a typical IC process, the control circuit and LDMOS can be integrated on a monolithic power IC. LDMOS The process uses reduced surface electric field (RESURE) technology and low-thickness epitaxy (EPI) or N-type well region (N-well), which can achieve high voltage and low on-resistance. [0003] The LDMOS device is a field-effect transistor device (FET)...

AI Technical Summary

Problems solved by technology

[0008] In practice, it is found that when the above-mentioned LDMOS transistor is applied to ESD protection, the protected element often cannot be turned on under the normal operating voltage (operate voltage)

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