Semiconductor device and method of operating the same
A method of operation, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problem of reducing the operating efficiency of devices
Active Publication Date: 2017-05-24
MACRONIX INT CO LTD
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- Application Information
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Problems solved by technology
In order to maintain the electrical performance of the semiconductor device, in operation, it is necessary to avoid the high voltage and leakage current in the high-voltage device area from affecting the low-voltage device, thereby reducing the operating performance of the device
Method used
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Embodiment Construction
[0038] Please refer to figure 1 , which shows a cross-sectional view of a semiconductor device according to an embodiment. The semiconductor device includes a first doped region 102, a second doped region 104, a first doped layer 106, a first doped contact 108, a second doped contact 110, a third doped contact 112 and a first gate structure 114 .
[0039] The first doped region 102 may include adjacent doped wells 116 and 118 . In one embodiment, the doped well 116 and the doped well 118 have a first conductivity type such as N conductivity type. Doped well 116 is, for example, a high voltage N-type well (HVNW).
[0040] The second doped region 104 may include an adjacent doped well 120, a buried doped layer 122, a doped well 124, a second doped layer 126, and a contact region 128, all of which have a second conductivity type opposite to the first conductivity type. For example P conductivity type. For example, the doped well 120 and the doped well 124 are high voltage P-...
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The invention discloses a semiconductor device and an operation method thereof. The semiconductor device comprises a first doped zone, a second doped zone, a first doped contact, a second doped contact, a first doped layer, a third doped contact and a first grid structure. The first doped zone is of a first conductive type; the second doped zone is adjacent to the first doped zone and is of a second conductive type opposite to the first conductive type; the first doped contact and the second doped contact are disposed on the first doped zone; a first PN junction is arranged between the first doped contact and the second doped contact; the first doped layer is disposed below the first doped contact or the second doped contact; the a second PN junction is arranged between the first doped layer and the first doped contact or the second doped contact and is adjacent to the first PN junction; the third doped contact is of the first conductive type and is configured in the second doped zone; and the first grid structure is configured on the second doped zone between the first doped zone and the third doped contact.
Description
technical field [0001] The present invention relates to a semiconductor device and its operating method, and more particularly to an insulated gate bipolar transistor (IGBT) device and its operating method. Background technique [0002] In recent decades, the semiconductor industry has continued to shrink the size of semiconductor devices while simultaneously improving speed, performance, density, and unit cost of integrated circuits. [0003] Shrinking the device area usually severely sacrifices the electrical performance of the semiconductor device. In order to maintain the electrical performance of the semiconductor device, in operation, it is necessary to prevent the high voltage and leakage current in the high voltage device area from affecting the low voltage device, thereby reducing the operating performance of the device. Contents of the invention [0004] According to one embodiment of the present invention, a semiconductor device is provided, which includes a fi...
Claims
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IPC IPC(8): H01L29/739H01L29/06H01L21/331
CPCH01L29/0603H01L29/0688H01L29/66325H01L29/7393
Inventor 蔡英杰陈永初龚正
Owner MACRONIX INT CO LTD