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Hardware on-chip storage method applicable to infra-frame prediction reference pixels in HEVC (high efficiency video coding) standard

A technology of reference pixel and intra-frame prediction, applied in the field of digital video, can solve the problems affecting resource occupation and coding efficiency, and achieve the effect of easy reading, speeding up reading, and reducing difficulty of reading

Inactive Publication Date: 2015-02-18
FUDAN UNIV
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Problems solved by technology

Therefore, the storage method for these reference pixels will directly affect the occupancy of resources and the efficiency of encoding

Method used

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  • Hardware on-chip storage method applicable to infra-frame prediction reference pixels in HEVC (high efficiency video coding) standard
  • Hardware on-chip storage method applicable to infra-frame prediction reference pixels in HEVC (high efficiency video coding) standard
  • Hardware on-chip storage method applicable to infra-frame prediction reference pixels in HEVC (high efficiency video coding) standard

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Embodiment Construction

[0027] The method of the present invention will be further specifically described below by way of examples and in conjunction with the accompanying drawings.

[0028] as for Figure 4 , for the 4×4 block marked A, its abscissa x- rd is 2, the ordinate y rd is 1. Then, according to the formula (1), the first address of the reference pixel to be read in the line memory is obtained Row_Addr rd is 1, and the remaining addresses are 2 and 3; according to the formula (2), the first address of the reference pixel to be read in the line memory is obtained Col_Addr rd is 16, and the remaining addresses are 17 and 18.

[0029] Another example is right Figure 5 , for the 8×8 block marked A, the abscissa of the 4×4 block in the upper left corner x- rd is 2, the ordinate y rd for 2. Then according to the formula (1), the first address of the required reference pixel in the line memory is obtained Row_Addr rd is 17, and the remaining addresses are 18, 19, 20, 21; accordi...

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Abstract

The invention belongs to the technical field of digital videos, and particularly relates to a hardware on-chip storage method applicable to infra-frame prediction reference pixels in the HEVC (high efficiency video coding) standard. In HEVC, the infra-frame prediction is executed based on executing of objects of blocks. Supposing the maximum unit of current codes is a 64*64 block including a total of 256 4*4 block bodies, 7 prediction pixels in each 4*4 block body serve as the reference pixels, and a storage space of at least 1792 pixels is needed. The reference pixels are separately stored in two storers, a line storer is used for storing the reference pixels, 1024 in total, on the upper right, the upside and the upper left; a column storer is used for storing the reference pixels, 1024 as well, on the upper left, the left side and the lower left; the access address is decided according to the positions of the corresponding 4*4 block bodies in the current 64*64 block. With the method, access capability of the reference pixels can be effectively improved, process time can be reduced, and real-time coding of the high-definition videos is realized.

Description

technical field [0001] The invention belongs to the technical field of digital video, and is aimed at the HEVC video codec standard, and in particular relates to a hardware on-chip storage method for reference pixels of intra-frame prediction in the HEVC standard. Background technique [0002] HEVC (High Efficiency Video Coding) is a next-generation video codec standard proposed by JCTVC, an organization jointly established by the International Telecommunications Organization (ITU) and the Motion Picture Experts Group (MPEG). The goal is to double the compression rate compared to the previous generation standard, namely the H.264 / AVC standard, on the premise of the same visual effect. [0003] The video encoder based on HEVC is mainly composed of the following modules: intra prediction, inter prediction, transformation, quantization, inverse quantization, inverse transformation, reconstruction, deblocking filter, adaptive sample point compensation, etc. Among them, the intr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N19/423H04N19/503
Inventor 范益波黄磊磊刘聪程魏曾晓洋
Owner FUDAN UNIV
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