Network chip temperature optimization method applied to two-dimensional grid structure piece

Abstract

The invention relates to a network chip temperature optimization method applied to a two-dimensional grid structure piece. The network chip temperature optimization method includes the following steps that 1, the relation between the communication task load among all inner cores and the temperature is worked out by inputting chip parameters and conducting formula computing to serve as the relation equation for calculating the temperature of the chip; 2, path distribution of communication tasks among all the inner cores is conducted by the adoption of a greedy algorithm, the chip temperature caused by the path distribution scheme serves as the ceiling temperature in the optimizing process; 3, all possible shortest paths are distributed to the communication tasks to be combined to different path distribution schemes, and the computing amount is reduced by weeding out the path distribution schemes which cannot meet the constrain conditions while path distribution is conducted; 4, the path distribution scheme of the minimum temperature value is used as the optimized result by computing the chip temperature of the path distribution scheme stored when the last communication task is distributed. According to the network chip temperature optimization method, the lower chip temperature is obtained without changing the chip performance, more communication tasks are made to use the communication paths higher in heat dissipation efficiency, and thus the temperature of the chip is reduced.

Description

technical field [0001] The invention relates to a temperature optimization method for a two-dimensional grid structure on-chip network chip. Background technique [0002] Compared with traditional bus-structured chips, two-dimensional grid (Mesh) network-on-chip chips can not only improve device integration, but also effectively shorten the length of connections, providing low-latency, high-bandwidth, and scalable The communication architecture improves the performance of the chip. However, with the improvement of chip integration, the power consumption of the chip continues to increase, and the temperature of the chip also continues to rise. The temperature has become one of the main factors affecting the performance of the chip. At present, the main methods to solve the chip temperature problem include improving the external heat dissipation efficiency of the chip, limiting the operating frequency of the chip, and reducing the voltage. [0003] The first method to improv...

AI Technical Summary

Problems solved by technology

However, operations such as limiting the frequency, reducing the voltage, and turning off the circuit logic will reduce the operating performance of the chip. This method is equivalent to exchanging the low performance of the chip for the low power consumption of the chip.

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