Network chip temperature optimization method applied to two-dimensional grid structure piece

A network chip and two-dimensional grid technology, applied in resource allocation, multi-programming devices, etc., can solve problems such as reducing chip operating performance

Active Publication Date: 2015-03-25
SHANGHAI INFOTM MICROELECTRONICS
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Problems solved by technology

However, operations such as limiting the frequency, reducing the voltage, and turning off the circuit logic will reduce the operating pe

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  • Network chip temperature optimization method applied to two-dimensional grid structure piece
  • Network chip temperature optimization method applied to two-dimensional grid structure piece
  • Network chip temperature optimization method applied to two-dimensional grid structure piece

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Embodiment Construction

[0035] The present invention will be further described below in conjunction with the accompanying drawings. Such as figure 1 As shown, the two-dimensional grid structure network-on-chip chip is constructed by multiple cores in a grid structure. Each core is at a fixed physical location, and the communication tasks between the cores must be completed through the transfer between the cores, so each communication task will select a communication path to complete the communication. Such as figure 1 , assuming that the position of the kernel 101 is (x 101 ,y 101 ), the position of the kernel 102 is (x 102 ,y 102 ), the communication task from the core 101 to the core 102 can choose three paths A, B, and C for communication, the length of the communication path is the number of cores passed, if the length of the communication path is equal to (|y 101 -y 102 |)+(|x 101 -x 102 |), then this path is called the shortest path of the communication task. figure 1 Both path A and ...

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Abstract

The invention relates to a network chip temperature optimization method applied to a two-dimensional grid structure piece. The network chip temperature optimization method includes the following steps that 1, the relation between the communication task load among all inner cores and the temperature is worked out by inputting chip parameters and conducting formula computing to serve as the relation equation for calculating the temperature of the chip; 2, path distribution of communication tasks among all the inner cores is conducted by the adoption of a greedy algorithm, the chip temperature caused by the path distribution scheme serves as the ceiling temperature in the optimizing process; 3, all possible shortest paths are distributed to the communication tasks to be combined to different path distribution schemes, and the computing amount is reduced by weeding out the path distribution schemes which cannot meet the constrain conditions while path distribution is conducted; 4, the path distribution scheme of the minimum temperature value is used as the optimized result by computing the chip temperature of the path distribution scheme stored when the last communication task is distributed. According to the network chip temperature optimization method, the lower chip temperature is obtained without changing the chip performance, more communication tasks are made to use the communication paths higher in heat dissipation efficiency, and thus the temperature of the chip is reduced.

Description

technical field [0001] The invention relates to a temperature optimization method for a two-dimensional grid structure on-chip network chip. Background technique [0002] Compared with traditional bus-structured chips, two-dimensional grid (Mesh) network-on-chip chips can not only improve device integration, but also effectively shorten the length of connections, providing low-latency, high-bandwidth, and scalable The communication architecture improves the performance of the chip. However, with the improvement of chip integration, the power consumption of the chip continues to increase, and the temperature of the chip also continues to rise. The temperature has become one of the main factors affecting the performance of the chip. At present, the main methods to solve the chip temperature problem include improving the external heat dissipation efficiency of the chip, limiting the operating frequency of the chip, and reducing the voltage. [0003] The first method to improv...

Claims

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Application Information

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IPC IPC(8): G06F9/50
Inventor 谢门旺金荣伟刘春晖林锦麟
Owner SHANGHAI INFOTM MICROELECTRONICS
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