A temperature optimization method applied to two-dimensional grid structure network-on-chip chip

A network chip, two-dimensional grid technology, applied in the direction of resource allocation, multi-programming device, etc., can solve problems such as reducing the running performance of the chip

Active Publication Date: 2017-12-26
SHANGHAI INFOTM MICROELECTRONICS
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Problems solved by technology

However, operations such as limiting the frequency, reducing the voltage, and turning off the circuit logic will reduce the operating performance of the chip. This method is equivalent to exchanging the low performance of the chip for the low power consumption of the chip.

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  • A temperature optimization method applied to two-dimensional grid structure network-on-chip chip
  • A temperature optimization method applied to two-dimensional grid structure network-on-chip chip
  • A temperature optimization method applied to two-dimensional grid structure network-on-chip chip

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Embodiment Construction

[0035] The present invention will be further described below in conjunction with the accompanying drawings. like figure 1 As shown, the two-dimensional grid structure network-on-chip chip is constructed by multiple cores in a grid structure. Each core is at a fixed physical location, and the communication tasks between the cores must be completed through the transfer between the cores, so each communication task will select a communication path to complete the communication. like figure 1 , assuming that the position of the kernel 101 is (x 101 ,y 101 ), the position of the kernel 102 is (x 102 ,y 102 ), the communication task from the core 101 to the core 102 can choose three paths A, B, and C for communication, the length of the communication path is the number of cores passed, if the length of the communication path is equal to (|y 101 -y 102 |)+(|x 101 -x 102 |), then this path is called the shortest path of the communication task. figure 1 Both path A and path B...

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Abstract

The present invention relates to a method for optimizing the temperature of a network-on-chip chip with a two-dimensional grid structure, including the following steps: Step 1: Calculate the relationship between the communication tasks and the temperature between each core by inputting chip parameters and calculating the temperature as a computing chip The relational equation of temperature; Step 2 is to assign the path of communication tasks between the cores by applying the greedy algorithm, and the chip temperature caused by the path assignment scheme is used as the upper limit temperature in the optimization process; Step 3, by assigning all possible communication tasks to the communication tasks The shortest path is combined into different path allocation schemes, and the path allocation schemes that do not meet the constraint conditions are eliminated during path allocation to reduce the amount of calculation; step 4, by calculating the chip temperature of the path allocation scheme saved when the last communication task is allocated, Take the path assignment scheme with the minimum temperature value as the optimization result. The present invention obtains a lower chip temperature under the condition that the chip performance remains unchanged, so that more communication tasks use a communication path with higher heat dissipation efficiency, thereby achieving the purpose of reducing the chip temperature.

Description

technical field [0001] The invention relates to a temperature optimization method for a two-dimensional grid structure on-chip network chip. Background technique [0002] Compared with traditional bus-structured chips, two-dimensional grid (Mesh) network-on-chip chips can not only improve device integration, but also effectively shorten the length of connections, providing low-latency, high-bandwidth, and scalable The communication architecture improves the performance of the chip. However, with the improvement of chip integration, the power consumption of the chip continues to increase, and the temperature of the chip also continues to rise. The temperature has become one of the main factors affecting the performance of the chip. At present, the main methods to solve the chip temperature problem include improving the external heat dissipation efficiency of the chip, limiting the operating frequency of the chip, and reducing the voltage. [0003] The first method to improv...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50
Inventor 谢门旺金荣伟刘春晖林锦麟
Owner SHANGHAI INFOTM MICROELECTRONICS
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