Clock pulse system, clock pulse integrated circuit and clock pulse generation method

Abstract

The clock pulse system, the clock pulse integrated circuit and the clock pulse generation method receive the reference clock signal through the alignment position to generate the functional clock pulse, and the functional clock pulse is provided to the functional circuit through the clock pulse path. The clock system includes a low-band PLL, a high-band PLL, and a delay path. The low frequency band PLL receives the reference clock signal and the feedback clock to provide the filtered clock. The high-band phase-locked loop receives the filter clock pulse and provides the functional clock pulse. The high-band phase-locked loop has a feedback input end coupled to the output end of the high-band phase-locked loop via a local feedback path. The delay path is coupled between the output end of the low-band PLL and the alignment position to provide a feedback clock pulse to the low-band PLL. The delay path substantially matches the clock path. The bandwidths of the low-band PLL and the high-band PLL are used to reduce input jitter and internal jitter, respectively.

Description

technical field [0001] The present invention relates to a clock pulse signal generation method and device, in particular to using a low-band phase-locked loop with a matching clock delay path to generate a low-jitter clock signal, and using at least one high-frequency phase-locked loop with a local feedback path loop to reduce jitter. Background technique [0002] Traditional clock pulse generation systems usually include at least one phase-locked loop, which is used to multiply the frequency of the reference clock pulse signal to generate one or more high-frequency clock pulse signals, which are used for synchronization or timing purposes and provided to integrated Functional circuits of circuits, semiconductor chips or similar devices. Each clock signal generated by the phase-locked loop is sent back to the feedback input end of the phase-locked loop for synchronizing the phase and frequency of the fed-back clock signal with the reference signal. Although the reference s...

AI Technical Summary

Problems solved by technology

Therefore, the designer of the phase-locked loop has to compromise between the bandwidth and the inability to reduce both kinds of jitter at the same time

Although input jitter as well as internal jitter may be reduced to some extent in frequency adjustment, the sum of the two jitters is still significant

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