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Semiconductor structure

A semiconductor and carrier technology, which is applied in the field of semiconductor structures with anti-stress regions, can solve the problems of general products having no suitable structure, inconvenience, and reducing the yield of semiconductor structures 200.

Inactive Publication Date: 2015-04-15
CHIPBOND TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] see Image 6 , an existing known semiconductor structure 200, which has a carrier 210, a first protection layer 220, a second protection layer 230 and a third protection layer 240, because the first protection layer 220, the second protection layer 230 and The third protection layer 240 is quadrilateral and the first protection layer 220, the second protection layer 230 and the third protection layer 240 are stacked on the carrier 210, so the stress of the semiconductor structure 200 is easy to concentrate on the The overlapping corners of the first passivation layer 220 and the second passivation layer 230 , so that the overlapping corners of the first passivation layer 220 and the second passivation layer 230 are broken or disconnected, thereby reducing the yield of the semiconductor structure 200
[0003] It can be seen that the above-mentioned existing semiconductor structure obviously still has inconvenience and defects in structure and use, and needs to be further improved urgently.
In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but for a long time no suitable design has been developed, and the general product has no suitable structure to solve the above-mentioned problems. This is obviously the relevant industry. Urgent problem

Method used

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Embodiment Construction

[0040] In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation, structure, characteristics and effects of a semiconductor structure proposed according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. , as detailed below.

[0041] see figure 1 and figure 2 , a semiconductor structure 100 having a corner 100a, the semiconductor structure 100 includes a carrier 110, a first protection layer 120, a second protection layer 130 and a third protection layer 140, the carrier 110 has a carrier surface 111, the carrier surface 111 has a protective layer setting area 111a and a protective layer exposed area 111b located outside the protective layer setting area 111a, the first protective layer 120 is set in the protective layer setting area 111a, the first protective layer 120 has a first surface 121, The f...

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Abstract

A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.

Description

technical field [0001] The present invention relates to a semiconductor structure, in particular to a semiconductor structure with an anti-stress region. Background technique [0002] see Image 6 , an existing known semiconductor structure 200, which has a carrier 210, a first protection layer 220, a second protection layer 230 and a third protection layer 240, because the first protection layer 220, the second protection layer 230 and The third protection layer 240 is quadrilateral and the first protection layer 220, the second protection layer 230 and the third protection layer 240 are stacked on the carrier 210, so the stress of the semiconductor structure 200 is easy to concentrate on the The overlapping corners of the first passivation layer 220 and the second passivation layer 230 are broken or disconnected at the overlapping corners of the first passivation layer 220 and the second passivation layer 230 , thereby reducing the yield of the semiconductor structure 200 ...

Claims

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Application Information

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IPC IPC(8): H01L29/06
CPCH01L23/31H01L23/3192H01L23/562H01L29/02H01L2924/0002H01L2924/00
Inventor 谢庆堂徐佑铭刘明昇王智平
Owner CHIPBOND TECH
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