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EEPROM durability test method and EEPROM durability test device

A technology to be tested for durability test, applied in static memory, instruments, etc., can solve the problem of long time

Inactive Publication Date: 2015-05-27
NO 47 INST OF CHINA ELECTRONICS TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The "read verification" and other status display time are not included here, and the durability test process is generally: erase-blank-check-write-read verification. If it is an extreme test, it will take longer

Method used

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  • EEPROM durability test method and EEPROM durability test device
  • EEPROM durability test method and EEPROM durability test device
  • EEPROM durability test method and EEPROM durability test device

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Embodiment Construction

[0042] Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0043] According to the solution of the present invention, aiming at the existing EEPROM durability test process "erase-blank check-write-read verification", the step of "blank check" is removed and parallel operation is introduced. see figure 1 , the EEPROM durability test method according to an embodiment of the present invention comprises the steps:

[0044] S1, build a matrix structure with M rows and N columns with M*N pipe positions. The pipe positions are used to insert the EEPROM to be tested. Each row of N pipe positions leads to a local data bus. M≥2 and is an integer, and N≥2 and It is an integer; the size of M and N is based on actual test needs, and the expansion is limited by the number of signals and the driving capability of the circuit. In this embodiment, both M and N are 4 (hereinafter both M and N=4 are taken as an example). In t...

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Abstract

The invention discloses an EEPROM (Electrically Erasable Programmable Read-Only Memory) durability test method which comprises the steps of establishing a matrix structure, and performing batch tests on to-be-tested EEPROMs on all pipe positions by taking 'erase-write in-read check' as a test period in one round. The method is improved based on the existing EEPROM durability test process, the step of 'blank check' is omitted, and parallel operation is introduced, so that full selection operation is realized during 'erase' and 'write in', and a check result is directly produced through preprocessing during 'read check' to realize column selection operation. The invention further discloses an EEPROM durability test device which comprises a matrix structure, a central processing unit, a logic control circuit, a data bus circuit and a latch. The parallel operation is used as much as possible in each link of 'erase-write in-read check', so that the time is saved effectively and the efficiency is improved effectively.

Description

technical field [0001] This application relates to the field of EEPROM (Electrically Erasable Programmable Read-Only Memory, Electrically Erasable Programmable Read-Only Memory) testing. Background technique [0002] EEPROM (Electrically Erasable Programmable Read-Only Memory) is a user-alterable read-only memory that can be erased and rewritten by the application of a higher than normal voltage. EEPROM durability refers to the ability of a device to withstand repeated erasing and writing. It is a key indicator of device performance and an important branch of reliability research and evaluation. [0003] The durability test is very time-consuming, and a test sometimes takes several weeks or even more. Take an example of 100,000 tests of 28C040 memory: the capacity of the chip is 256K, that is, 1024 pages, the page writing time is 10ms, and the chip erasing time is 20ms. The time consumed for erasing and writing: (20+10*1024)*100000ms=1026*1000s. About 285 hours. The "read...

Claims

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Application Information

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IPC IPC(8): G11C29/56
Inventor 赵德权李翠于祥苓常宏伟戴俊夫裴志强
Owner NO 47 INST OF CHINA ELECTRONICS TECH GRP
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