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Memory device

A storage device and vertical column technology, applied in information storage, static memory, read-only memory, etc., can solve problems such as affecting the integration of 2D or planar storage devices, limiting the integration of 2D or planar storage devices, and being expensive.

Active Publication Date: 2015-05-27
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the fine patterning technique used in the device can affect the integration of 2D or planar memory devices
However, the process equipment used to increase the fineness of the pattern will be very expensive, so it will actually limit the improvement of the integration of 2D or planar memory devices

Method used

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Embodiment Construction

[0058] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments of the inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, And these embodiments will fully convey the concept of example embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. The same reference numerals in the drawings denote the same elements, and thus their descriptions will be omitted.

[0059] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when...

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Abstract

Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

Description

[0001] This patent application claims priority from Korean Patent Application No. 10-2013-0140672 filed in the Korean Intellectual Property Office on Nov. 19, 2013, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] The present disclosure herein relates to a semiconductor device, and in particular, to a vertical type memory device. Background technique [0003] Higher integration of semiconductor devices is desired to meet the demand for high-performance and low-cost electronic devices. In particular, the integration of storage devices can affect product prices. The degree of integration of a typical two-dimensional (2D) or planar memory device can be determined by the area occupied by a unit memory cell. Therefore, the fine patterning technique used in the device can affect the integration of 2D or planar memory devices. However, the process equipment for increasing the fineness of the pattern is very expensive, thus actu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L45/00G11C16/00
CPCH10B41/27
Inventor 薛光洙姜真泰曹盛纯
Owner SAMSUNG ELECTRONICS CO LTD
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