Electronic igniter of gas equipment

[0009] The present invention will be further explained below in conjunction with the drawings:

[0010] Such as figure 1 As shown, the present invention includes a first switch S1, a second switch S2, a third switch S3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. , Seventh resistor R7, eighth resistor R8, first diode D1, second diode D2, third diode D3, fourth diode D4, fifth diode D5, sixth diode Tube D6, discharge tube Z, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, fifth capacitor C5, first NAND gate X1, second NAND gate X2, third NAND Gate X3, fourth NAND gate X4, relay K and thyristor DT, the voltage input end of the power supply is connected to the first end of the first switch S1, and the second end of the first switch S1 is connected to the second end of the first resistor R1 , The first end of the first resistor R1 is simultaneously connected to the first end of the first capacitor C1, the first end of the second resistor R2, the first end of the relay K and the first end of the relay switch K1-1 of the relay K , The second end of the first capacitor C1 is simultaneously connected to the cathode of the first diode D1, the second end of the second resistor R2 and the anode of the second diode D2, and the anode of the first diode D1 is simultaneously connected to the The first end of the second switch S2, the second end of the second capacitor C2 and the second end of the thyristor DT are connected, the second end of the second switch S2 is connected to the voltage output end of the power supply, and the cathode of the second diode D2 is simultaneously Connected to the first terminal of the second capacitor C2, the voltage input terminal of the fourth NAND gate X4, the first terminal of the fifth capacitor C5 and the first terminal of the eighth resistor R8, the relay switch K1-1 of the relay K The second end is connected to the first end of the first winding of the transformer T, the second end of the first winding of the transformer T is grounded, and the second end of the second winding of the transformer T is simultaneously connected to the third diode D3 The cathode is connected to the anode of the fourth diode D4, and the second end of the second winding of the transformer T is simultaneously connected to the cathode of the sixth diode D6 and the anode of the fifth diode D5. The fourth diode D4 The cathode of is connected to the cathode of the fifth diode D5 and the first end of the fourth resistor R4 at the same time, and the second end of the fourth resistor R4 is simultaneously connected to the first end of the fifth resistor R5 and the first end of the third capacitor C3. Connected to the first end of the discharge tube Z, the second end of the discharge tube Z is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is simultaneously connected to the second end and the fifth resistor of the third capacitor C3 The second terminal of R5, the anode of the sixth diode D6, and the anode of the third diode D3 are connected to the signal output terminal L, the control terminal of the thyristor DT is connected to the first terminal of the third resistor R3, and the third resistor R3 The second end of the first NAND gate X1 and the first end of the second NAND gate X2 are connected at the same time, and the first output end of the first NAND gate X1 is simultaneously connected to the first end of the first NAND gate X1. Two output terminals, the first output terminal of the second NAND gate X2 and the second output terminal of the second NAND gate X2, the first terminal of the third NAND gate X3 and the second output terminal of the fourth NAND gate X4 Connected, the first output terminal of the third NAND gate X3 is simultaneously connected to the first terminal of the fourth capacitor C4, the first terminal of the seventh resistor R7 and the third NAND gate X3 The second output terminal is connected, the second terminal of the seventh resistor R7 is grounded, the second terminal of the fourth capacitor C4 is connected to the first terminal of the fourth NAND gate X4, and the ground terminal of the fourth NAND gate X4 is grounded. The second output terminal of the NAND gate X4 is simultaneously connected to the second terminal of the fifth capacitor C5, the first terminal of the third switch S3 and the second terminal of the eighth resistor R8, and the second terminal of the third switch S3 is grounded.