Shallow trench isolation structure thinning method

Abstract

The invention provides a shallow trench isolation structure thinning method. The shallow trench isolation structure thinning method comprises the steps: S1, a tunneling oxidation layer, shallow trench isolation structures and floating gates are manufactured on a semiconductor substrate and the semiconductor substrate is divided into a storage unit zone and a peripheral circuit zone; S2, the shallow trench isolation structures in the storage unit zone and the peripheral circuit zone are etched and thinned and openings are formed in the positions where the etched shallow trench isolation structures are located; S3, ONO layers are formed on the surfaces of the floating gates and the surfaces of the shallow trench isolation structures in the storage unit zone and the peripheral circuit zone; S4, the ONO layers and the floating gates in the peripheral circuit zone are etched and removed; S5, the shallow trench isolation structures in the peripheral circuit zone are etched and thinned. In addition, the shallow trench isolation structures in the storage unit zone and the peripheral circuit zone are etched and thinned, a thinning process is simplified, and trenches are effectively prevented from being formed in two sides of the top of each shallow trench isolation structure under the protection effect of the ONO layers during follow-up etching.

Description

Technical field [0001] This application relates to the field of semiconductor manufacturing technology, and in particular, to a method for thinning a shallow trench isolation structure. Background technique [0002] With the advancement of semiconductor manufacturing technology, shallow trench isolation (STI) has gradually replaced isolation methods such as local silicon oxidation used in traditional semiconductor device manufacturing. Shallow trench isolation has many advantages compared with other isolation methods, including: STI can obtain a narrower semiconductor device isolation width, thereby improving device integration; STI can improve device surface flatness, so it can be effectively controlled during photolithography The minimum line width. [0003] Because the memory cell area I and the peripheral circuit area II of the flash memory need to be operated during the use of the semiconductor device, and different areas require different operating conditions, the design rul...

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Problems solved by technology

[0011] The purpose of this application is to provide a thinning method for shallow trench isolation structures, so as to solve the problem of edge trenches on the top of shallow trench isolation structures in the prior art

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