Thinning Method of Shallow Trench Isolation Structure

Abstract

The present application provides a method for thinning a shallow trench isolation structure. The thinning method includes: step S1, forming a tunnel oxide layer, a shallow trench isolation structure, and a floating gate on a semiconductor substrate, and dividing the semiconductor substrate into a memory cell area and a peripheral circuit area; step S2, etching and thinning the memory cell area and the shallow trench isolation structure in the peripheral circuit area, forming an opening at the position of the etched shallow trench isolation structure; step S3, forming an ONO on the surface of the floating gate and the shallow trench isolation structure in the memory cell area and the peripheral circuit area layer; step S4, etching and removing the ONO layer and the floating gate in the peripheral circuit area; and step S5, etching and thinning the shallow trench isolation structure in the peripheral circuit area. At the same time, the shallow trench isolation structure in the memory cell area and the peripheral circuit area is etched and thinned, which simplifies the thinning process; the subsequent etching is under the protection of the ONO layer, which effectively avoids the top sides of the shallow trench isolation structure. The emergence of grooves.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a method for thinning a shallow trench isolation structure. Background technique [0002] With the advancement of semiconductor manufacturing technology, shallow trench isolation (STI) has gradually replaced isolation methods such as local silicon oxidation methods used in traditional semiconductor device manufacturing. Compared with other isolation methods, shallow trench isolation has many advantages, mainly including: STI can obtain a narrower semiconductor device isolation width, thereby improving device integration; STI can improve device surface flatness, so it can be effectively controlled during lithography. Minimum line width. [0003] Since the memory cell area I and its peripheral circuit area II of the flash memory need to be operated during the use of semiconductor devices, and different areas require different operating conditions...

AI Technical Summary

Problems solved by technology

[0011] The purpose of this application is to provide a thinning method for shallow trench isolation structures, so as to solve the problem of edge trenches on the top of shallow trench isolation structures in the prior art

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