Dynamic release method and system of register file cache resources and processor

Abstract

The invention provides a dynamic release method and system of register file cache resources and a processor. The real-time detection can be performed on a long-time delay event under the condition that instructions are not increased or changed, a register file cache table item by which a thread of the long-time delay event is occupied is sent and marked as a preferred replacement request when the long-time delay event is detected, the register file cache table item by which the thread is occupied can be timely marked as the preferred replacement through register file caches after the request is received, the thread can be replaced out in a preferred mode if registers of other threads need to be called into the register file caches from a main register file, and the other threads are not affected. Compared with the prior art, the monitoring on the long-time delay event is sensitive, the instructions do not need to be adjusted, and the efficiency of release recycling on the register file cache resources is high.

Description

technical field [0001] The invention relates to the technical field of multi-thread processor design, in particular to a method and system for dynamically releasing register file cache resources and a processor. Background technique [0002] The register file of a multi-threaded processor usually adopts a multi-level register file structure design, including the main register file MRF (Main Register File); and the register file cache RFC (Register File Cache). [0003] The main register file is used to store the general-purpose registers of all threads. It has a large capacity, but its ports are limited and its speed is relatively slow. The register file cache has many ports and is fast, but the capacity is small. Generally, only 2-3 general-purpose registers are reserved for each thread. When the register that a certain thread needs to read is not in the register file cache but in the main register file, the register needs to be retrieved from the main register file to the...

AI Technical Summary

Problems solved by technology

[0005] (1) The instructions recognized by the compiler in the static compilation phase are too general, because system instructions and memory access instructions often appear in the instruction stream, but they do not necessarily cause long-delay pauses

If the execution results of all these instructions are not written back to the register file cache but directly written back to the main register file, it will seriously affect the execution efficiency of the thread and it is a waste of register file cache resources

[0006] (2) Static compilation needs to add some Hint type bits to the instructions to tell the hardware that these instructions need to bypass the register file cache, which is equivalent to adding new instructions and will also affect thread execution efficiency.

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