Fabrication method of photolithography mark in epitaxial process

Abstract

The invention discloses a method for manufacturing a photolithographic mark in an epitaxial process. The steps include: 1) forming a barrier layer on a substrate, and defining a photolithographic mark region by photolithography; 2) forming a photolithographic mark on the barrier layer, The depth of the photolithography mark is less than the thickness of the barrier layer, using the photolithography mark to define the pattern of the groove, and opening the barrier layer in the groove area; 3) etching the groove on the substrate, the first Secondary selective epitaxial growth and CMP; 4) Removing the barrier layer outside the photolithography marked area; 5) Second epitaxial growth and CMP; 6) Opening the photolithographic marked area by photolithography and epitaxial etching. The present invention uses a barrier layer between the substrate and the epitaxial growth layer to protect the photolithography mark area, and opens the photolithography mark area by etching the epitaxial layer after the epitaxial growth, thereby ensuring the shape of the photolithography mark and the subsequent photolithography Alignment accuracy.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit technology manufacturing, in particular to a method for making a photoetching mark applied in an epitaxy (EPI) growth technology. Background technique [0002] The Super Junction (Super Junction) structure in Power MOSFET (Power Metal Oxide Semiconductor Field Effect Transistor) is an innovative structure on the withstand voltage layer, which has the characteristics of low on-resistance, high withstand voltage and low heat generation, and Overcome the "silicon limit" of conventional MOSFETs. It often uses the epitaxial process to withstand high voltage, adopts vertical conduction and double diffusion structure (such as figure 1 shown). In the manufacture of the new generation of SJ MOSFET devices, it is necessary to etch the deep trench first and fill the P column, and then form a 20-40 μm epitaxial layer through the second deposition. [0003] Overlay accuracy is an important ch...

AI Technical Summary

Problems solved by technology

Epitaxy often produces defects such as haze, slip lines, stacking faults, punctures, etc., which have a great impact on lithographic alignment

Especially after the epitaxial growth of 20-40um in the new generation of SJ MOSFETs, if the general photolithographic mark production method is used, that is, the photolithographic mark is made first and then the epitaxial growth is used, the photolithographic mark will be very seriously distorted or even disappear, and it will be completely impossible. alignment (eg figure 2 shown)

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