A ate-based fpga device testing system and method

Abstract

The invention relates to a FPGA device test system based on ATE and a method thereof. The system comprises a test control device, a waveform conversion device and a test monitoring and display device. The test control device controls an excitation control signal and inputs the signal to a tested FPGA device through the waveform conversion device. The FPGA device receives the excitation control signal and outputs a corresponding output signal according to the excitation control signal. The waveform conversion device converts the excitation signal emitted by the test control device into an input waveform file and transmits the waveform file to the tested FPGA device. The waveform conversion device converts the output signal into a waveform signal. The test monitoring and display device outputs and displays the waveform signal and compares the output waveform signal to an expected waveform signal so as to output a comparison result. By using the system and the method in the invention, a physical test platform with high reliability is realized, wherein precision of the platform can reach over nanosecond.

Description

technical field [0001] The invention relates to an ATE-based FPGA device testing system and method. Background technique [0002] FPGA devices have the characteristics of high integration, high speed, high reliability, and low power consumption, and have been widely cited in aerospace and other fields. At present, the main methods of FPGA device behavior testing are functional testing through register transfer level simulation and timing testing through post-layout simulation. Since the test environment covered by the simulation test is relatively ideal, it cannot truly reflect the operating characteristics of FPGA devices and devices interacting with FPGAs under actual physical conditions, such as device voltage characteristics, level conversion characteristics, actual delay information of cross-linked devices, board Interconnect delay information, etc., so a physical test method must be sought to test the FPGA. [0003] In the FPGA chip, the target code actually appears ...

AI Technical Summary

Problems solved by technology

Since the test environment covered by the simulation test is relatively ideal, it cannot truly reflect the operating characteristics of FPGA devices and devices interacting with FPGAs under actual physical conditions, such as device voltage characteristics, level conversion characteristics, actual delay information of cross-linked devices, board Interconnect delay information, etc., so a physical test method must be found to test the FPGA

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