A Programmable SRAM Synchronous Clock Control Module Circuit

Abstract

The invention relates to a programmable static random access memory synchronous clock module circuit, which belongs to the field of integrated circuit design. The circuit includes: the module circuit includes 9 inverters composed of NMOS transistors and PMOS transistors, 1 two-input NAND gate, 2 two-input NOR gates, 2 transmission gates, 1 by 4 inverters Inverter cascaded buffer module composed of inverters in series, a clock encoding circuit; this module can automatically generate the required sense amplifier enable signal, bit line precharge signal, drive decoder output word according to different read and write operations line signal, transient negative bit line enable signal, etc., greatly simplifying the difficulty of SRAM timing control. Different operation timings are achieved through peripheral signal control, which also simplifies the difficulty of timing control.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and relates to a programmable SRAM synchronous clock control module circuit, in particular to a delay chain structure and programmable design. Background technique [0002] With the development of process size and the improvement of integration, in order to save power consumption, future SRAM designs will work at lower operating voltages. However, the lower operating voltage will directly lead to the increase of circuit logic delay, which further complicates the timing design of the circuit, especially for a circuit system with a lot of control signals such as SRAM. Therefore, it is desirable to have a synchronous clock control module. When the SRAM is performing read and write operations, the clock module will generate all the enable signals required for the operation by delaying the trigger on the rising edge of the clock. At the same time, for the row-column decoder of the SR...

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Problems solved by technology

[0004] Finally, for the existing synchronous clock control module circuit, the controllability of the SRAM working timing is relatively lacking

The timing of SRAM needs to measure the read and write speed of SRAM in many aspects. In order to avoid the delay of the actual synchronous clock control module circuit being higher than the result of the simulation due to process deviation or circuit parasitic effects, it is necessary to leave a certain amount of redundancy. The magnitude of this redundancy is difficult to control. Too much reservation will affect the operating frequency of the synchronous clock control module circuit, and too low reservation may directly cause the synchronous clock control module circuit to fail to work correctly.

However, the timing setting of the existing synchronous clock control module circuit is fixed and immutable, which greatly reduces the flexibility and brings difficulties to the implementation of SRAM

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