Programmable static random access memory synchronous clock control module circuit

Abstract

The invention relates to a programmable static random access memory synchronous clock control module circuit and belongs to the technical field of integrated circuit design. The module circuit comprises 9 inverters composed of NMOS pipes and PMOS pipes, a two-input NAND gate, two two-input nor gates, two transmission gates, an inverter cascade buffer module formed by connecting fur inverter in series and a clock encoding circuit and can automatically generate required sense amplifier enable signals, bit line precharge signals, driving decoder output word line signals, transient negative bit line enable signals according to different read-write operations, and the like and greatly simplify SRAM timing sequence control difficulty. Different time sequential routines can be realized through peripheral signal control, so that the sequential control difficulty is simplified.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and relates to a programmable SRAM synchronous clock control module circuit, in particular to a delay chain structure and programmable design. Background technique [0002] With the development of process size and the improvement of integration, in order to save power consumption, future SRAM designs will work at lower operating voltages. However, the lower operating voltage will directly lead to the increase of circuit logic delay, which further complicates the timing design of the circuit, especially for a circuit system with a lot of control signals such as SRAM. Therefore, it is desirable to have a synchronous clock control module. When the SRAM is performing read and write operations, the clock module will generate all the enable signals required for the operation by delaying the trigger on the rising edge of the clock. At the same time, for the row-column decoder of the SR...

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Problems solved by technology

[0004] Finally, for the existing synchronous clock control module circuit, the controllability of the SRAM working timing is relatively lacking

The timing of SRAM needs to measure the read and write speed of SRAM in many aspects. In order to avoid the delay of the actual synchronous clock control module circuit being higher than the result of the simulation due to process deviation or circuit parasitic effects, it is necessary to leave a certain amount of redundancy. The magnitude of this redundancy is difficult to control. Too much reservation will affect the operating frequency of the synchronous clock control module circuit, and too low reservation may directly cause the synchronous clock control module circuit to fail to work correctly.

However, the timing setting of the existing synchronous clock control module circuit is fixed and immutable, which greatly reduces the flexibility and brings difficulties to the implementation of SRAM

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