memory circuit

Abstract

The invention provides a memory circuit which comprises a first memory unit and a second memory unit, each of which comprises a source electrode and a drain electrode, a first bit line decoding circuit, a second bit line decoding circuit, a sense amplifier and a first voltage following circuit, wherein a first end of the first bit line decoding circuit is electrically connected with a drain electrode of the first memory unit and a source electrode of the second memory unit, a first end of the second bit line decoding circuit is electrically connected with a drain electrode of the second memory unit, the sense amplifier is electrically connected with a second end of the first bit line decoding circuit and is suitable for amplifying read current passing through the first bit line decoding circuit, the input end of the first voltage following circuit is electrically connected with a second end of the first bit line decoding circuit, the output end of the first voltage following circuit is electrically connected with the second end of the second bit line decoding circuit, and the voltage of the output end of the first voltage following circuit is lower than that of the input end of the first voltage following circuit. For the memory circuit, electricity leakage at the side edge during the reading process is small, and the accuracy is high.

Description

Technical field [0001] The present invention relates to the field of semiconductors, and in particular to a memory circuit. Background technique [0002] Semiconductor memory is an important part of digital integrated circuits, and they play a vital role in building microprocessor-based application systems. The performance of the memory array and its peripheral circuits largely determines the operating conditions of the entire system, including speed and power consumption. [0003] Flash memory has become a research hotspot in non-volatile memory due to its convenience, high storage density, and good reliability. A typical flash memory includes a memory cell array, which has many memory cells arranged in rows and columns. Each memory cell is manufactured as a field effect transistor with a control gate and a floating gate. The floating gate is used to retain charge and is isolated from the source and drain regions contained in the substrate by a thin oxide layer. This memory ce...

AI Technical Summary

Problems solved by technology

[0005] The problem to be solved by the present invention is that when the memory cell in the prior art reads data, there is the problem of inaccurate read current

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