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Lattice mismatched heterojunction structures and devices made therefrom

A heterojunction and band structure technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as limitations

Active Publication Date: 2015-11-18
WISCONSIN ALUMNI RES FOUND
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Unfortunately, these shortcomings of epitaxial growth and wafer bonding techniques have limited the number of material combinations that can be incorporated into semiconductor heterojunction structures

Method used

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  • Lattice mismatched heterojunction structures and devices made therefrom
  • Lattice mismatched heterojunction structures and devices made therefrom
  • Lattice mismatched heterojunction structures and devices made therefrom

Examples

Experimental program
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Embodiment

[0061] This example describes the image 3 and 4 Fabrication of back-to-back heterojunction structures of HBT devices.

[0062] In this fabrication scheme, a collector layer comprising n-type GaAs, a base layer comprising p-type Si, and an emitter layer comprising n-type GaAs are each fabricated separately before being incorporated into a vertical HBT structure.

[0063] To form GaAs current collectors, GaInP / GaAs / GaAsnpn-type HBTs were obtained from Kopin / Skyworks. as in Figure 13 As shown in , the HBT starts with a 9-layer structure. Layers 1-5 are removed, leaving a GaAs-containing substrate ( Figure 13 Layer 9 in), n-type GaAs sub-collector ( Figure 13 layer 8) and the n-type GaAs current collector ( Figure 13 A 4-layer current collector stack of layers 6 and 7) in ( Figure 13 Layers 6-9 in; in Figure 14 correspond to reference numerals 1412-1418, respectively). (It should be noted that in this experiment, a prefabricated HBT was used as the starting substra...

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Abstract

Semiconductor heterojunction structures comprising lattice mismatched, single-crystalline semiconductor materials and methods of fabricating the heterojunction structures are provided. The heterojunction structures comprise at least one three-layer junction comprising two layers of single-crystalline semiconductor and a current tunneling layer sandwiched between and separating the two layers of single-crystalline semiconductor material. Also provided are devices incorporating the heterojunction structures, methods of making the devices and method of using the devices.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Patent Application No. 13 / 831,449, filed March 14, 2013, which is hereby incorporated by reference in its entirety. Background technique [0003] Semiconductor heterojunctions and the devices incorporating them are key components of the semiconductor industry. Conventional heterojunctions are formed by epitaxial growth of lattice-mismatched or nearly lattice-mismatched materials together with their growth substrates. Thus, epitaxial growth techniques require the grown material to acquire the same structure and crystallographic orientation as the growth substrate. Large lattice mismatches between materials in successive layers in epitaxially grown heterostructures will lead to the formation of dislocations, leading to failed devices. [0004] Another technique for fabricating heterostructures of different materials is wafer bonding. However, conventional wafer bonding requires the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/20
CPCH01L29/1602H01L29/267H01L29/66242H01L29/7371H01L29/861H01L33/04
Inventor Z·马J-H·徐
Owner WISCONSIN ALUMNI RES FOUND