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Apparatus and method for detecting clock tampering

A clock and tampering technology, applied in error detection/correction, non-redundancy-based fault handling, generation of response errors, etc., can solve problems such as increasing clock frequency and shortening computing time

Inactive Publication Date: 2015-11-25
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Also, an attack may increase the clock frequency to shorten the computation period sufficiently that incorrect values ​​of incomplete computations are sampled in registers of the computing system

Method used

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  • Apparatus and method for detecting clock tampering
  • Apparatus and method for detecting clock tampering
  • Apparatus and method for detecting clock tampering

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Embodiment Construction

[0023] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other embodiments.

[0024] refer to figure 1 , 2 and 3, aspects of the present invention may reside in a method 100 for detecting clock tampering. In the method, a plurality of resettable delay line segments 210 are provided (step 110). The resettable delay line segments between the resettable delay line segment 210-1 associated with the minimum delay time and the resettable delay line segment 210-N associated with the maximum delay time are each associated with a discretely increasing delay time . Monotonic signal 220 is provided during clock evaluation period 310 associated with clock CLK (step 120). The monotonic signal is delayed using each of the plurality of resettable delay line segments to produce a corresponding plurality of delayed monotonic sig...

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Abstract

Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.

Description

technical field [0001] The present invention generally relates to detecting tampering with a clock and / or supply voltage of a processor. Background technique [0002] Cryptographic calculations of computing systems can be attacked by causing temporary spikes (or glitches) on clock and / or supply voltages, thereby introducing glitches into the calculation results. Also, an attack may increase the clock frequency to shorten the calculation period sufficiently that incorrect values ​​of incomplete calculations are sampled in registers of the computing system. Additionally, the attack may slow down the computing system's bus to make it easier to attack the system. [0003] There is therefore a need for a technique for detecting tampering with respect to a processor's clock and / or supply voltage in an efficient and cost-effective manner. Contents of the invention [0004] Aspects of the invention may reside in a method for detecting clock tampering. In the method, a plurality...

Claims

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Application Information

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IPC IPC(8): G06F21/72G06F11/07G06F1/04
CPCG06F21/57G06F1/04G06F11/0721G06F11/076G06F21/725G06F1/06G06F21/00G06F21/55G06F21/602G06F21/70G06F21/71
Inventor 克里斯·蒂里马修·斯科特·麦格雷戈陶宇聪
Owner QUALCOMM INC