A memory testing device and a memory chip testing method

Abstract

The invention provides a memorizer testing device and a memorizer chip testing method. The relation that address spaces of invalid address memorizers of traditional memorizer testing instruments correspond to address spaces of tested chips one to one is changed. The address spaces of the invalid address memorizers are segmented into continuous stored record units. Each stored record unit does not store address data of bits passing tests any more and only stores address data of bits failing to pass the tests, including home addresses of quad-side contact where the stored invalid bits are located, relative addresses in the quad-site contact where the invalid bits are located in chips, address information in the chips where the invalid bits are located and the like. In this way, in the memorizer function testing process, invalid information of multiple chips are stored at the same time, and the utilization rate and the testing speed of invalid address hardware storage spaces are greatly increased.

Description

Technical field [0001] The invention relates to the technical field of semiconductor testing, in particular to a memory testing device and a memory chip testing method. Background technique [0002] The birth of chips (or integrated circuits, ICs) has prompted human society to enter a colorful era of digitization, informationization, and intelligence. Computers, mobile phones, digital cameras, high-definition digital TVs, automobile electronic controls, navigation systems, medical equipment, ordnance equipment..., chips are everywhere. In the process of rapid development of chips toward high integration (LSI, VLSI), high speed, and high performance, humans' pursuit of perfect chips has become more and more intense. However, in the real world, in the design, processing, manufacturing and production of integrated circuits, various human and non-human factors lead to errors that are unavoidable. These errors cause waste of resources and dangerous accidents. Personal injury and deat...

AI Technical Summary

Problems solved by technology

[0003] 1. Due to the one-to-one correspondence between AFM and DUT addresses, this requires the same capacity of AFM and DUT, which makes AFM very expensive

[0004] 2. In general, the failure address of a DUT is much smaller than its capacity, and the traditional failure address storage method, even if only one bit (Bit) of the tested DUT fails, AFM must specially set aside a space equal to the capacity of the DUT To correspond with the DUT one by one, and carry out the identification operation of all addresses of the DUT, so that the information is not effectively recorded in the AFM, and the utilization rate of the AFM hardware storage space is very low

thus greatly affecting the test speed

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