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A Variable Length Radar Pulse Data Buffering Method

A technology of radar data and radar pulses, which is applied in electrical digital data processing, memory systems, instruments, etc., and can solve problems such as data loss, data storage errors, and time instability

Active Publication Date: 2018-01-12
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the pulse repetition period length of the radar pulse signal is not fixed, the time for storing a set of pulse data is not fixed, and the traditional ping-pong buffer method cannot meet the requirements for accurate data storage
Two kinds of errors usually occur: when the length of data in the ping-pong buffer storage area A being written is less than the length of the data read from the ping-pong buffer storage area B, in the case that the data in the buffer B is not read completely , the read-write switch of the ping-pong buffer will be switched, which will cause data loss; The data in the memory may cause data storage errors due to the superposition of two data

Method used

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  • A Variable Length Radar Pulse Data Buffering Method
  • A Variable Length Radar Pulse Data Buffering Method
  • A Variable Length Radar Pulse Data Buffering Method

Examples

Experimental program
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Embodiment Construction

[0028] The non-destructive buffering method of variable-length radar echo data based on FPGA is used to simulate the situation that the period of the pulse signal in the environment where the radar transmits the pulse signal remains unchanged, becomes longer and shorter. Proceed as follows:

[0029] Step 1. Set the sizes of single-port RAM buffer areas A and B to meet the maximum radar pulse period. The write control module connects the input data interface to buffer area A, and the read control module connects the output data interface to buffer area B. Determine the parameters m and n according to the radar performance, so that the radar pulse period length can be reduced then read the time Then wait for the arrival of the pulse detection signal. Among them, l is the length of the radar pulse period, and △l is the variation of the radar pulse period length; t is the time required to read the data whose radar pulse period length is l under the system clock Clock; △t is t...

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Abstract

The invention discloses a variable-length radar pulse data buffering method, which belongs to the signal processing technology, and particularly relates to the data buffering technology. The device used in the method includes a radar pulse detection module, a data writing control module, a data reading control module, a single-port RAM buffer area and a writing address register. In this method, the clock of writing the cache is twice the input clock, writing data and clearing alternately, and storing the address at the end of the data in the write address register as the calculation source of the end address of the read module. The read clock is m times the input clock, and the read bit width is n times the data bit width. As a result, the reading speed is much higher than the writing speed. In this way, the correct buffering method can be achieved without clearing the entire block after the radar pulse cycle changes.

Description

technical field [0001] The technical field of data signal processing of the present invention specifically refers to buffering of baseband variable-length radar pulse data. Background technique [0002] Data caching is a basic operation in the field of signal processing. When storing or computing a large amount of real-time data, it is usually necessary to cache first to ensure correct data processing. [0003] In the real-time storage of radar and its analog echo signals, the traditional method is to use a fixed-length ping-pong buffer area to ping-pong buffer and store the data, and then transmit the buffered data to a large-capacity storage device. The cache ping-pong operation is to allocate the data stream isochronously to two data buffer storage areas of the same size: the first buffer cycle stores the input data into the buffer storage area A. In the second buffering cycle, data is input to the buffer storage area B, and at the same time, the cached data in the buffe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0877
Inventor 周云祖东辉卢霞霞周杨鹏汪学刚
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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