Three-dimensional semiconductor device and manufacture method thereof

Abstract

Provided is a three-dimensional semiconductor device which comprises multiple storage units. Each storage unit comprises a channel layer stack, multiple insulated layers, multiple gate conductive layers, a gate dielectric layer, a drain, and a source. The channel layer stack is distributed along the direction vertical to the surface of a substrate. The multiple insulated layers and the multiple gate conductive layers are stacked alternately along the sidewall of the channel layer stack. The gate dielectric layer is arranged between the multiple gate conductive layers and the sidewall of the channel layer stack. The drain is arranged on the top of the channel layer stack. The source is arranged in the substrate between two adjacent storage units of the multiple storage units. The lowest insulated layer is provided with an obtuse or rounded corner portion. According to the three-dimensional semiconductor device and a manufacture method thereof, the closed angle of a transistor on the bottom is made obtuse or rounded in order to suppress a local electric field enhancement effect so that a gate dielectric electric field of the transistor on the bottom is uniformly distributed and reliability is improved.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional semiconductor storage device and a manufacturing method thereof. Background technique [0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] Specifically, such as Figure 1A As shown, a multi-layer stack structure (for example, multiple ONO structures al...

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Problems solved by technology

At this time, this non-90-degree etching will cause serious sharp corner problems in the L-type transistor. There will be a local strong electric field in this area, which will make the gate dielectric very prone to breakdown, thereby deteriorating reliability.

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