Page or word-erasable composite non-volatile memory

Abstract

The disclosure provides a page or word-erasable composite non-volatile memory. The non-volatile memory includes bit lines, a first page-erasable sector including memory cells of a first type, and a second word-erasable or bit-erasable sector including memory cells of a second type. The memory cells of the first type comprise a single floating-gate transistor and the memory cells of the second type comprise a first floating-gate transistor and a second floating-gate transistor the floating gates of which are electrically coupled, the second floating-gate transistor of a memory cell of the second type enabling the memory cell to be individually erased.

Description

technical field [0001] This disclosure relates to non-volatile memory and in particular to memory arrays and memory cell structures of the type described in US Application 2013 / 0228846, which is incorporated herein by reference in its entirety. Background technique [0002] As a reminder, figure 1 This memory array structure MA0 is represented and two adjacent physical pages P, here belonging to the memory array, of the corresponding ranks "i" and "i-1" are shown. i ,P i-1 The above type of memory cell M i,j , M i-1,j , M i,j+1 , M i-1,j+1 . memory cell M i,j , M i-1,j , M i,j+1 , M i-1,j+1 is through the bit line BL j 、BL j+1 , word line WL i-1,i and the control gate line CGL i 、CGL i-1 Read-accessible and program-accessible. Each memory cell includes floating gate transistors, respectively T i,j , T i-1,j , T i,j+1 , T i-1,j+1 . Transistor T i,j , T i-1,j The drain terminal D is connected to the bit line BL j and the transistor T i,j+1 , T i-1,j+1...

AI Technical Summary

Problems solved by technology

This significantly complicates the word line and column decoders and will involve providing various voltage switches within each page to control the different word control gate lines

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