Adaptive Timing for A/D Conversion

Abstract

This application relates to adaptive timing for analog-to-digital conversion. An analog-to-digital conversion system and method includes, for example, a comparator X1 (see paragraph A) for sampling an analog quantity during a sampling period [222] and for converting the sampled analog quantity during a conversion period [222] A series of bit-wise conversions [212] are performed on an analog sample of , where each bit-wise conversion occurs during a corresponding bit-wise conversion cycle [230], wherein successive bits of the sample are successively determined during the corresponding bit conversion cycle, and where the execution of A predetermined number of bitwise conversions [eg, number of cycles in 212]. A clock generator [400] is arranged for generating a clock signal [210] for clocking said converter [138] during said conversion cycle, wherein each bit conversion cycle [230] comprises A reset period [232] of a second length and an amplification period [234] of a second length, wherein one of the first and second lengths is dynamically selected.

Description

technical field [0001] This application relates to adaptive timing for analog-to-digital conversion. Background technique [0002] A successive approximation register (SAR) analog-to-digital converter (ADC) serially determines each bit of the sampled value. The ADC clock signal is used to drive the SAR ADC operation. The frequency of the ADC clock signal varies with the sampling frequency and number of cycles required for each sample. Generally, an ADC clock signal is derived from a phase locked loop (PLL) formed in a substrate of a system on chip (SOC). However, with the limited frequency selection available from a PLL (eg, previously described) designed into the SOC, it is often difficult to achieve a frequency for optimal switching for various applications. Contents of the invention [0003] The above-mentioned problems can be addressed in analog / digital systems and methods that include, for example, comparators that perform a series of sequential bit conversion, wh...

AI Technical Summary

Problems solved by technology

However, with the limited frequency selection available from the PLL designed into the SOC (eg, previously described), it is often difficult to achieve the frequency for optimal switching for various applications

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