Cavity forming method and semiconductor device structure
A cavity, N-type technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to achieve the effect of simple process and low cost
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Embodiment 1
[0050] refer to Figure 1a As shown, an N-type doped silicon substrate 100 is provided. The silicon substrate 100 is, for example, a silicon substrate with a crystal orientation of , which facilitates the formation of a single crystal silicon layer with better quality. The N-type doped silicon substrate 100 is preferably a lightly doped (N-) substrate, and the doping concentration is, for example, less than 10 18 cm -3 , but not limited to this.
[0051] refer to Figure 1b As shown, N-type impurity ions are implanted into a predetermined area on the front side of the silicon substrate 100, and then an N-type heavily doped (N+) doped region 101 is formed through an annealing process. The N-type impurity ions are, for example, phosphorus ions, The annealing temperature is, for example, 900-1100°C, preferably 1000°C, the annealing time is, for example, 40-60 minutes, preferably 50 minutes, and the doping concentration of the N+ doped region 101 is preferably greater than 10 ...
Embodiment 2
[0060] refer to Figure 2a As shown, an N-type doped silicon substrate 200 is provided. The N-type doped silicon substrate 200 is preferably a lightly doped (N-) substrate, and the doping concentration is, for example, less than 10 18 cm -3 , but not limited to this.
[0061] refer to Figure 2b As shown, N-type impurity ions are implanted into a local area on the front side of the silicon substrate 200, and then an N+ doped area 201 is formed through a high temperature annealing process. While ion implantation is performed in a local area on the front side of the silicon substrate 200, N-type impurity ions are also implanted in the entire back area of the silicon substrate 200, and an N+ doped region 202 is formed on the back side of the silicon substrate 200 through a high temperature annealing process.
[0062] refer to Figure 2c As shown, the N+ doped region 201 on the front side of the silicon substrate 200 is converted into a porous silicon layer 203 by means of ...
Embodiment 3
[0069] This embodiment provides a semiconductor device structure, which can be formed by using the method described in Embodiment 1 or Embodiment 2. refer to Figure 1g shown, combined with Figure 1a-1f As shown, the semiconductor device structure includes: an N-type doped silicon substrate 100; a cavity 103' formed in the front surface of the silicon substrate 100; a single crystal silicon formed on the front surface of the silicon substrate 100 layer 104; a via hole 104' formed in said monocrystalline silicon layer 104 and exposing said cavity 103'.
[0070] Further, the semiconductor device structure further includes a film layer 105 formed on the single crystal silicon layer 104 and closing the cavity 103'.
[0071] Wherein, the silicon substrate 100 is N-type lightly doped, and the doping concentration of the silicon substrate is less than 10 18 cm -3 . The cross-sectional shape of the through hole 104' is a rectangle, and the longitudinal cross-sectional shape of t...
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